“To look at people in capitalist society and conclude that human nature is egoism is like looking at people in a factory where pollution is destroying their lungs and saying that it is human nature to cough”

I wish you good.

Just a snek on the internet | Call me Doppler (or just Snek) | He/they | Forever in love with my Cuddlefish 🖤🩶🤍💜

People keep asking me, and I haven't really had an answer, but now yeah, I'm thinking I'm back.

Life is beautiful

AuDHD ♾️ Queer 💜 FOSS enthusiast 👩‍💻 anarcho-trotskiest 🏴🛠️ (actually just an antisectarian ecosocialist who is naive enough to believe in socialist unity)

You die twice. One time when you stop breathing, and a second time, a bit later on, when somebody damns your soul for the last time.

• Hafez Al-Assad

Basically a deer with a human face. Despite probably being some sort of magical nature spirit, his interests are primarily in technology and politics and science fiction.

Spent many years on Reddit before joining the Threadiverse as well.

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Array operator at ASO.

You might also know me as Dr. Kel or Kellin.

if youre on bluesky follow @ap.brid.gy or i cant see your posts and interactions

Podbicia, pomoc, pierdółwpis.

Podbijam wpisy z polskiego #fediwersum. Rzucam hasztagami. Oprowadzę po fedi i odpowiem na pytania go dotyczące. #fediTipsPL #FediPomoc

Piszę głównie po polsku, ale inne języki raczej zrozumiem (sprawdź, czy poprawnie go oznaczasz).

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Zobacz tylko moje autorskie wpisy: https://justmytoots.com/@[email protected]

He/Him

Sneaking all around the fediverse.

Also at:
[email protected]
[email protected]
[email protected]

rawdog meatspace cooperator eating digital vegetal. systems/neuro & digital infrastructure for information liberation by day, p2p and broken shit by night and also by day. lookin 2 eat the rich n abolish intellectual property.

This is my personal account, for more science/academic oriented things i use https://neuromatch.social/@jonny

no longer accepting follow requests on this account unless we know each other already <3. send me a dm if we know each other and you're using a pseud

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Don't comply
Odznaczona orderem Virtuti cebulari

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Embrace What Makes You Happy.

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Bay Area, Nara · dangillmor.com

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Reality is Analog. All else is fantasy.

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I write, make, draw, play, game, and do handsome faces. I made Hive Time. Currently making Fossil Sweeper (a game about digging up fossils), Winter's Wake & Icicle (and a stack of side things).

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This account is strictly SFW. I don't make or boost NSFW stuff.

#nobot

Send me asks with valid VHDL, SystemVerilog, Amaranth, Spade, or Veryl code and I will execute it for you on a real FPGA!

You can send me asks from outside Wafrn by sending me a direct message (private mention) in the following format: "!ask icepi-zero-bot " followed by your code.

If your instance has a character limitations, you can split your code into a thread of multiple direct messages. In this case, first send your code as multiple direct messages without the "!ask" prefix and then respond to the last message with a direct message containing only "!ask icepi-zero-bot ". I will recognize the empty ask, fetch the entire thread, and use the entire text (excluding all mentions) as source code.

All successful responses are public and include your submitted code. Only submit code you are happy to share with the world.

For any questions/problems with this bot, please contact jcm or [email protected].

Examples / Templates

VHDL ```
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
generic(
WIDTH : integer := 640;
HEIGHT : integer := 480;
CONSOLE_COLUMNS : integer := WIDTH / 8;
CONSOLE_ROWS : integer := HEIGHT / 8
);
port(
clk : in std_logic;
rst : in std_logic;

    px : in integer range 0 to WIDTH - 1;
    py : in integer range 0 to HEIGHT - 1;
    hsync : in std_logic;
    vsync : in std_logic;

    col : in integer range 0 to CONSOLE_COLUMNS - 1;
    row : in integer range 0 to CONSOLE_ROWS - 1;

    char : out integer range 0 to 127 := 0;
    foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
    background_color : out std_logic_vector(23 downto 0) := (others => '1')
);

end my_code;

architecture rtl of my_code is
alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16);
alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0);

signal frame_counter : unsigned(31 downto 0) := (others => '0');

constant example_text : string(1 to 19) := "Hello Fediverse! <3";
constant example_text_row : integer := 15;
constant example_text_col : integer := 15;

begin
char <= character'pos(example_text(col + 1 - example_text_col))
when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

red   <= std_logic_vector(to_unsigned(col*4, 8));
green <= std_logic_vector(to_unsigned(py, 8));
blue  <= std_logic_vector(resize(frame_counter, 8));

foreground_color <= (others => '1');

process(clk)
    variable old_vsync : std_logic := '0';
begin
    if rising_edge(clk) then
        if vsync = '0' and old_vsync = '1' then
            frame_counter <= frame_counter + 1; 
        end if;
        old_vsync := vsync;
    end if;
end process;

end architecture;

 **SystemVerilog** ```
module my_code #(
    parameter int WIDTH = 640,
    parameter int HEIGHT = 480,
    parameter int CONSOLE_COLUMNS = WIDTH / 8,
    parameter int CONSOLE_ROWS = HEIGHT / 8
)(
    input  logic clk,
    input  logic rst,

    input  int px,
    input  int py,
    input  logic hsync,
    input  logic vsync,

    input  int col,
    input  int row,

    output int char,
    output logic [23:0] foreground_color,
    output logic [23:0] background_color
);
    logic [31:0] frame_counter = '0;
    logic old_vsync = '0;

    logic [7:0] red, green, blue;

    always_comb begin
        red   = 8'(col * 4);
        green = 8'(py);
        blue  = frame_counter[7:0];

        background_color = {red, green, blue};
        foreground_color = '1;

        char = 0;
    end

    always_ff @(posedge clk) begin
        if (vsync == 1'b0 && old_vsync == 1'b1) begin
            frame_counter <= frame_counter + 1;
        end

        old_vsync <= vsync;
    end
endmodule

Amaranth ```
from amaranth import *

class MyCode(Elaboratable):
def init(self, width, height, console_columns, console_rows):
self.WIDTH = width
self.HEIGHT = height
self.CONSOLE_COLUMNS = console_columns
self.CONSOLE_ROWS = console_rows

    self.px = Signal(signed(32), name="px")
    self.py = Signal(signed(32), name="py")
    self.hsync = Signal(name="hsync")
    self.vsync = Signal(name="vsync")

    self.col = Signal(signed(32), name="col")
    self.row = Signal(signed(32), name="row")

    self.char = Signal(signed(32), name="char")
    self.foreground_color = Signal(24, name="foreground_color")
    self.background_color = Signal(24, name="background_color")

def elaborate(self, platform):
    m = Module()

    frame_counter = Signal(32)
    old_vsync = Signal()

    red = Signal(8)
    green = Signal(8)
    blue = Signal(8)

    m.d.comb += [
        red.eq(self.col * 4),
        green.eq(self.py),
        blue.eq(frame_counter),

        self.background_color.eq(Cat(blue, green, red)),
        self.foreground_color.eq(0xFFFFFF),
        self.char.eq(0)
    ]

    m.d.sync += old_vsync.eq(self.vsync)
    with m.If(~self.vsync & old_vsync):
        m.d.sync += frame_counter.eq(frame_counter + 1)

    return m

 **Spade** ```
#[no_mangle(all)]
entity my_code(
    clk: clock,
    rst: bool,
    px: int<32>,
    py: int<32>,
    hsync: bool,
    vsync: bool,
    col: int<32>,
    row: int<32>,
    char: inv &int<32>,
    foreground_color: inv &uint<24>,
    background_color: inv &uint<24>,
) {
    set char = &0;
    set foreground_color = &0xFFFFFFu24;
    set background_color = &0xFF7AFFu24;
}

Veryl ```
module my_code #(
param WIDTH: u32 = 640,
param HEIGHT: u32 = 480,
param CONSOLE_COLUMNS: u32 = WIDTH / 8,
param CONSOLE_ROWS: u32 = HEIGHT / 8
) (
clk: input clock,
rst: input reset,

px: input u32,
py: input u32,
hsync: input logic,
vsync: input logic,

col: input u32,
row: input u32,

char: output u32,
foreground_color: output logic<24>,
background_color: output logic<24>

) {
var frame_counter: u32;
var old_vsync: logic;

// Use logic<8> to facilitate easy concatenation later
var red: logic<8>;
var green: logic<8>;
var blue: logic<8>;

always_comb {
    // Cast math results to 'u8' (truncation). 
    // Veryl allows assigning u8 to logic<8>.
    red   = (col * 4) as u8;
    green = py as u8;
    blue  = frame_counter as u8;

    // Concatenate logic<8> elements directly
    background_color = {red, green, blue};
    foreground_color = 24'hff_ff_ff;

    char = 0;
}

always_ff (clk, rst) {
    if_reset {
        frame_counter = 0;
        old_vsync = 0;
    } else {
        if !vsync && old_vsync {
            frame_counter = frame_counter + 1;
        }
        old_vsync = vsync;
    }
}

}

 **You need to keep the same entity name and interface (generics and ports) as in the examples or the synthesis won't work!**