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Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.

Author's Latest Posts

Verifying Networks On Chip
By Ed Sperling - 20 Jul, 2026 - Comments: 0

More data, more processing elements, and more memories are making it much harder to maintain consistent throughput in a multi-die assembly. There is more concurrent traffic, more potential interactions, and more protocol layers. Ashish Darbari, CEO of Axiomise, talks about the of coherency on serialization bugs, how to ensure data is secure, and how to ferret out the root cause of problems like... » read more

AI In Chip Design: Lots Of Promise, Plenty Of Unanswered Questions
By Ed Sperling - 15 Jul, 2026 - Comments: 0

Key Takeaways: AI opens the door to exploring a much larger solution space, similar to what high-level synthesis did years ago, but questions persist about the impact of increasing reliance on what is essentially a black-box chip design. There is no consistent answer to how successful AI will be, where it will succeed or fail, or how it will apply to different markets and EDA customers.... » read more

AI Models On The Edge
By Ed Sperling - 14 Jul, 2026 - Comments: 0

Moving from large language models in the cloud to small language models at the edge is much more complicated than just slimming down the algorithms. It requires changes in both hardware and software, and the constraints can vary greatly from one market segment to another. Daniel Firu, CPO and co-founder of Quadric, and Ravi Chakaravarthy, vice president of software at the company, talk about ho... » read more

EDA/SIP Revenue Up 12.7%; APAC Roars Back
By Ed Sperling - 13 Jul, 2026 - Comments: 1

Worldwide EDA, semiconductor IP, and services revenue reached $5.748 billion in Q1 2026, a 12.7% increase compared to the same period in 2025. The key driver continues to be demand for tools used to create AI server chips, with computer-aided engineering up 15.5% to $2.018 billion. There was a noticeable bump in Chinese sales due to a relaxation of export restrictions, rising 31% to $508 mil... » read more

Executive Outlook: Agentic AI’s Impact On Chip Design
By Ed Sperling - 25 Jun, 2026 - Comments: 1

Key Takeaways: Agentic AI has the potential to make engineers more productive, speed time to market, and automate some of the drudge work. The big challenge for design and verification engineers is where and whether they trust AI to get everything right, because there is no margin for error in semiconductors. Having humans in the loop will likely be the rule rather than the exception... » read more

How Far Left Can You Shift?
By Ed Sperling - 24 Jun, 2026 - Comments: 0

More steps in the design flow are shifting left, which makes a complicated design process even more complex. This includes early software prototyping, workload mapping, verification, multi-physics integration, verification, IP qualification. Frank Schirrmeister, executive director of strategic programs for System Solutions at Synopsys, talks about the increasing number of steps, the potential t... » read more

New USB Standards: Benefits And Incompatibilities
By Ed Sperling - 23 Jun, 2026 - Comments: 0

Just because it's a standard doesn't mean everything will work together, and this is especially evident with conflicting USB standards. David Shin, senior product marketing manager at Cadence Design Systems, explains where incompatibilities can crop up, why it's so difficult to control the different versions, and what's behind all this confusion. » read more

Will Your Chip’s Memory Work As Expected?
By Ed Sperling - 22 Jun, 2026 - Comments: 0

Increased density at advanced nodes, multi-die assemblies, and the rollout of AI everywhere are making it much more challenging to ensure that memory will function properly over its expected lifetime. Test is no longer about a single memory or one approach for testing memory. It can vary by application, by workload, and by architecture. Some testing is close to memory, some is built into memory... » read more

Signoff Of Synthesis-Optimized Registers
By Ed Sperling - 17 Jun, 2026 - Comments: 0

How do you know when you sign off on a complex chip design that everything is going to work? There are more variables, more elements that need to be verified, and more waivers that need to be generated. Suresh Barla, senior director of field applications at Synopsys, talks about how to ensure that RTL is fully optimized for PPA targets in large designs that can include hundreds of millions of g... » read more

Wi-Fi Flies Higher As Edge AI Build-Out Takes Root
By Ed Sperling - 15 Jun, 2026 - Comments: 0

Key Takeaways: Wi-Fi 7 is becoming an essential technology for edge AI, and subequent demands for even better reliability will grow as the edge build-out takes shape. Edge computing is based on the assumption that more data will be processed and stored locally, which will help reduce data leakage and theft. The big challenge ahead will be orchestrating data movement across different ... » read more

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