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authorTakashi Kokubun <[email protected]>2023-02-28 23:22:12 -0800
committerTakashi Kokubun <[email protected]>2023-03-05 23:28:59 -0800
commitb5fbc9f59f760f5faaca82c5b2bc869a6f38ade5 (patch)
tree34e58c7ae16e9c38a916e60171629e0e23407441 /lib/ruby_vm/mjit/assembler.rb
parentfb08b0e748549959cd6eeaa7f4bc1babd9125557 (diff)
Implement ISEQ block_handler
Notes
Notes: Merged: https://github.com/ruby/ruby/pull/7448
Diffstat (limited to 'lib/ruby_vm/mjit/assembler.rb')
-rw-r--r--lib/ruby_vm/mjit/assembler.rb10
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/ruby_vm/mjit/assembler.rb b/lib/ruby_vm/mjit/assembler.rb
index 989d069776..aa3bc72bab 100644
--- a/lib/ruby_vm/mjit/assembler.rb
+++ b/lib/ruby_vm/mjit/assembler.rb
@@ -667,6 +667,16 @@ module RubyVM::MJIT
def or(dst, src)
case [dst, src]
+ # OR r/m64, imm8 (Mod 11: reg)
+ in [Symbol => dst_reg, Integer => src_imm] if r64?(dst_reg) && imm8?(src_imm)
+ # REX.W + 83 /1 ib
+ # MI: Operand 1: ModRM:r/m (r, w), Operand 2: imm8/16/32
+ insn(
+ prefix: REX_W,
+ opcode: 0x83,
+ mod_rm: ModRM[mod: Mod11, reg: 1, rm: dst_reg],
+ imm: imm8(src_imm),
+ )
# OR r64, r/m64 (Mod 01: [reg]+disp8)
in [Symbol => dst_reg, Array[Symbol => src_reg, Integer => src_disp]] if r64?(dst_reg) && r64?(src_reg) && imm8?(src_disp)
# REX.W + 0B /r