| Branch | Commit message | Author | Age | |
|---|---|---|---|---|
| master | Merge pull request #79 from bdunahu/bdunahu | Siddarth Suresh | 8 months | |
| Age | Commit message | Author | ||
| 2025-05-11 | Merge pull request #79 from bdunahu/bdunahuHEADmaster | Siddarth Suresh | ||
| 2025-05-11 | Add ROTV instruction | bd | ||
| 2025-05-11 | Fix bug where vector registers were not cleared when length was 0 | bd | ||
| 2025-05-11 | Stride load, stride store | bd | ||
| 2025-05-11 | Add I_VECT field type for SRDL, SRDS, with two vector reg 1 general | bd | ||
| 2025-05-11 | Remove I_VECT field types | bd | ||
| 2025-05-11 | Replaced STOREV with LOADV | bd | ||
| 2025-05-11 | Merge pull request #78 from bdunahu/bdunahu | Siddarth Suresh | ||
| 2025-05-10 | Fix bug where too many vector elements were written back | bd | ||
| 2025-05-10 | Fix off-by-one in CEV equal | bd | ||
| [...] | ||||
| Clone | ||||
| https://git.operationnull.com/RISC-VECTOR.git | ||||
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index : RISC-VECTOR.git | |
| A simulator for the custom RISC-V[ECTOR] ISA written in C++ | bd |
| summaryrefslogtreecommitdiff |