Ignore:
Timestamp:
Aug 16, 2003, 6:59:22 PM (22 years ago)
Author:
bird
Message:

binutils v2.14 - offical sources.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • branches/GNU/src/binutils/include/opcode/ppc.h

    • Property cvs2svn:cvs-rev changed from 1.1 to 1.1.1.2
    r608 r609  
    11/* ppc.h -- Header file for PowerPC opcode table
    2    Copyright 1994, 1995, 1999, 2000 Free Software Foundation, Inc.
     2   Copyright 1994, 1995, 1999, 2000, 2001, 2002
     3   Free Software Foundation, Inc.
    34   Written by Ian Lance Taylor, Cygnus Support
    45
     
    9091
    9192/* Opcode is supported by Altivec Vector Unit */
    92 #define PPC_OPCODE_ALTIVEC   (01000)
     93#define PPC_OPCODE_ALTIVEC (01000)
     94
     95/* Opcode is supported by PowerPC 403 processor.  */
     96#define PPC_OPCODE_403 (02000)
     97
     98/* Opcode is supported by PowerPC BookE processor.  */
     99#define PPC_OPCODE_BOOKE (04000)
     100
     101/* Opcode is only supported by 64-bit PowerPC BookE processor.  */
     102#define PPC_OPCODE_BOOKE64 (010000)
     103
     104/* Opcode is only supported by Power4 architecture.  */
     105#define PPC_OPCODE_POWER4 (020000)
     106
     107/* Opcode isn't supported by Power4 architecture.  */
     108#define PPC_OPCODE_NOPOWER4 (040000)
     109
     110/* Opcode is only supported by POWERPC Classic architecture.  */
     111#define PPC_OPCODE_CLASSIC (0100000)
     112
     113/* Opcode is only supported by e500x2 Core.  */
     114#define PPC_OPCODE_SPE     (0200000)
     115
     116/* Opcode is supported by e500x2 Integer select APU.  */
     117#define PPC_OPCODE_ISEL     (0400000)
     118
     119/* Opcode is an e500 SPE floating point instruction.  */
     120#define PPC_OPCODE_EFS      (01000000)
     121
     122/* Opcode is supported by branch locking APU.  */
     123#define PPC_OPCODE_BRLOCK   (02000000)
     124
     125/* Opcode is supported by performance monitor APU.  */
     126#define PPC_OPCODE_PMR      (04000000)
     127
     128/* Opcode is supported by cache locking APU.  */
     129#define PPC_OPCODE_CACHELCK (010000000)
     130
     131/* Opcode is supported by machine check APU.  */
     132#define PPC_OPCODE_RFMCI    (020000000)
    93133
    94134/* A macro to extract the major opcode from an instruction.  */
     
    123163     can accept any value).  */
    124164  unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
     165
    125166                                   const char **errmsg));
    126167
     
    142183     this operand (i.e., the instruction does not match).  If the
    143184     operand is valid, *INVALID will not be changed.  */
    144   long (*extract) PARAMS ((unsigned long instruction, int *invalid));
     185  long (*extract) PARAMS ((unsigned long instruction, int dialect,
     186                           int *invalid));
    145187
    146188  /* One bit syntax flags.  */
     
    231273#define PPC_OPERAND_VR (010000)
    232274
     275
     276
    233277
    234278
Note: See TracChangeset for help on using the changeset viewer.