Wafer-level packaging (WLP) is an advanced semiconductor packaging technology that encapsulates and interconnects integrated circuits (ICs) directly at the wafer level, prior to dicing the wafer into individual dies, enabling chip-scale dimensions and streamlined manufacturing.^[1] This process contrasts with traditional die-level packaging by applying protective layers, redistribution layers (RDL) for rerouting electrical connections, and solder bumps or balls across the entire wafer, which supports higher integration density and reduces overall package size to near the die footprint.^[2] Key variants include fan-in WLP, where connections are confined within the die area, and fan-out WLP, which expands connections beyond the die using a larger interposer or molded compound for increased input/output (I/O) density.^[3] The technology originated with wafer-level chip-scale packaging (WLCSP) entering high-volume manufacturing around 2000, evolving from earlier flip-chip and wire-bonding methods to address limitations in electrical performance and interconnect density.^[4] Fan-out WLP gained prominence in 2009 with Infineon's embedded wafer-level ball grid array (eWLB), marking a shift toward heterogeneous integration for multi-die systems.^[4] Core processes involve photolithography for patterning RDL, sputtering and electroplating for metal layers, dielectric deposition for insulation, and underfill or molding for protection, often culminating in solder ball attachment before singulation.^[3] Advanced implementations incorporate through-silicon vias (TSVs) for vertical stacking in 2.5D or 3D configurations, enhancing signal integrity and thermal management.^[4] WLP offers significant advantages, including reduced form factor for compact devices, lower production costs through wafer-scale processing and testing, and superior electrical and thermal performance due to shorter interconnect paths.^[1] It is widely adopted in mobile handsets (accounting for approximately 90% of such applications as of 2021), automotive electronics, Internet of Things (IoT) devices, and 5G infrastructure, where miniaturization and high I/O counts are critical.^[4] As of 2025, adoption is accelerating in artificial intelligence (AI) and high-performance computing (HPC) applications, driven by needs for advanced heterogeneous integration and chiplet architectures.^[5] However, challenges persist, such as managing wafer warpage during thinning, ensuring die alignment in fan-out processes, and achieving finer RDL pitches below 1 micrometer for high-end applications.^[4] Ongoing innovations, including panel-level extensions and embedded bridges, continue to expand WLP's role in enabling chiplet-based architectures and system-in-package (SiP) solutions.^[1]

Overview

Definition and principles

Wafer-level packaging (WLP) is an integrated circuit (IC) packaging technique in which all packaging steps, including electrical connections, redistribution of input/output (I/O) pads, and protective encapsulation, are performed at the wafer scale prior to the singulation of individual dies.^[6] This approach maintains the devices in their wafer form throughout the packaging process, enabling the creation of chip-scale packages that closely match the size of the die itself.^[6] Unlike conventional packaging methods that handle individual dies after dicing, WLP leverages semiconductor fabrication infrastructure to integrate packaging directly with front-end processing.^[7] The core principles of WLP revolve around the redistribution of I/O connections through redistribution layers (RDL), which reroute peripheral bond pads to an array across the full die area, facilitating higher I/O density and enabling compact, chip-scale form factors suitable for advanced electronics.^[6] This redistribution contrasts sharply with traditional die-level packaging, where processes such as wire bonding or flip-chip assembly occur on singulated dies, often requiring additional handling and leading to larger package sizes and lower throughput.^[7] By processing the entire wafer simultaneously, WLP achieves economies of scale, reduces manufacturing steps, and minimizes material waste, while supporting finer interconnect pitches driven by the same lithography tools used in IC fabrication.^[6] Key components of WLP include under bump metallization (UBM), which provides adhesion and barrier layers for solder joints on the redistributed pads, typically with thicknesses ranging from 1.5 to 30 μm; solder bumps, which form the external electrical interfaces with diameters up to 75 μm; and passivation layers, such as polyimides or photosensitive benzocyclobutene (PBO), that protect the wafer surface and RDL from environmental factors during and after processing.^[6] The scaling of interconnect pitch in RDL is fundamentally limited by lithography resolution, where the minimum pitch approximates the sum of line width and space, often achieving 10-50 μm in standard processes to balance density and yield.^[6] For instance,

$$\text{minimum pitch} \approx (\text{line width} + \text{space})$$

This relationship underscores how WLP's efficiency stems from aligning packaging with the precision of wafer-scale lithography, enabling high-volume production of miniaturized packages.^[7]

Importance in semiconductor manufacturing

Wafer-level packaging (WLP) plays a pivotal role in semiconductor manufacturing by enabling chip-scale packages (CSPs) where the package footprint closely matches the die size, achieving significant volume reductions compared to traditional wire-bonded packages through the elimination of substrates and leadframes.^[4] This miniaturization supports the ongoing trend toward smaller, more integrated devices in mobile, IoT, and automotive applications, where space constraints are critical.^[6] Economically, WLP drives cost efficiencies by performing packaging operations at the wafer level in batches, reducing assembly costs relative to conventional methods and facilitating high-volume production.^[8][9] These savings arise from streamlined testing and logistics, as final inspections occur pre-dicing, while the technology extends Moore's Law principles through efficient 3D integration without proportional increases in fabrication expenses.^[4] In terms of performance, WLP enhances signal integrity by employing shorter interconnects via redistribution layers (RDL), which minimize parasitic effects and reduce inductance, enabling higher operating frequencies and better electrical efficiency.^[6] Additionally, it provides thermal advantages through direct heat dissipation paths from the die to the board, lowering thermal resistance compared to wire-bonded or flip-chip BGA alternatives.^[10] WLP's scalability is evident in its support for heterogeneous integration in system-in-package (SiP) designs, allowing the combination of dies from different process nodes—including sub-10 nm technologies—with passives and interposers to overcome traditional packaging limitations in advanced architectures.^[4][6] This capability addresses the challenges of integrating diverse components for high-performance computing and 5G applications, promoting more modular and cost-effective scaling.^[11]

History

Early developments

The roots of wafer-level packaging (WLP) trace back to mid-20th-century innovations in flip-chip technology, particularly IBM's Solid Logic Technology (SLT) introduced in the early 1960s for the System/360 mainframe computers. SLT employed solder bumps on transistors, using Ni/Au-plated copper balls embedded in Sn-Pb solder on three I/O pads, with a Cr-Cu-Au adhesion layer between Al-Si pads and the bumps, allowing three chips to be assembled on a ceramic substrate via wafer-level processing.^[12] This approach marked an early precursor to WLP by enabling direct chip-to-substrate connections without wire bonds, addressing limitations in packaging density for integrated circuits.^[13] Building on SLT, IBM advanced the concept in the late 1960s with Controlled Collapse Chip Connection (C4), which utilized high-lead solder bumps deposited via electrochemical processes on wettable metal terminals, achieving pad sizes of about 100 μm and bump heights of 100 μm for simultaneous reflow of all joints.^[12] By the 1980s, C4 had evolved to support wafer-scale bumping with under-bump metallurgy like Ti/Cu or TiW/Cu, facilitating higher I/O counts and scalable area array interconnections that laid groundwork for full WLP by maintaining standoff and alignment through solder surface tension confined by passivation layers.^[13] These developments shifted focus from individual die handling to wafer-level operations, reducing assembly costs and improving reliability for emerging portable electronics that demanded smaller, more efficient packages over traditional wire bonding.