The common-source amplifier is a fundamental configuration in field-effect transistor (FET) circuits, where the source terminal is grounded or serves as the common connection for both the input signal applied to the gate and the output signal taken from the drain, enabling voltage amplification of small AC signals superimposed on a DC bias while operating the FET in the saturation region.[1][2] This setup inverts the phase of the output signal by 180 degrees relative to the input, providing a negative voltage gain typically greater than 1 in magnitude, such as -4.26 in example circuits.[1][3]Key characteristics include a high input impedance, often in the range of several kiloohms to megohms due to the insulating gate structure of FETs, which minimizes loading on preceding stages, and a moderate output impedance determined by the drain resistor and the FET's output resistance.[1][2] The small-signal voltage gain is given by $ A_v = -g_m (R_D \parallel r_o) $, where $ g_m $ is the transconductance (e.g., $ g_m = 2 K_n (V_{GS} - V_t) $ for MOSFETs), $ R_D $ is the drain load resistor, and $ r_o $ is the FET's output resistance.[1][2]Biasing is achieved using a DC supply $ V_{DD} $ and gate-source voltage $ V_{GS} $ to set the quiescent point (Q-point) midway in the saturation region for linear operation, ensuring the drain current $ I_D $ remains stable against variations.[3][2]This configuration offers advantages such as simplicity in design, suitability for integrated circuits due to efficient transistor usage over resistors, and effective linear amplification for applications like audio and RF signal processing.[1][2] Compared to other FET amplifiers like common-drain (source follower) or common-gate, the common-source provides the highest voltage gain but with the phase inversion, making it ideal for stages requiring signal boosting without buffering.[1] In practice, coupling capacitors are employed to isolate AC signals from DC bias, focusing operation in the mid-band frequency range for optimal performance.[2]
Circuit Configuration
Basic Topology
The common source amplifier is a fundamental configuration of a field-effect transistor (FET) amplifier in which the source terminal serves as the common connection for both input and output signals.[4] This topology is typically implemented using metal-oxide-semiconductor field-effect transistors (MOSFETs) or junction field-effect transistors (JFETs), providing high input impedance due to the insulated or reverse-biased gate.[5]In the standard schematic, the input signal is applied to the gate terminal, the output is extracted from the drain terminal, and the source is grounded or connected to a common reference point. A drain resistor $ R_D $ connects the drain to the positive supply voltage $ V_{DD} $, setting the DC load and enabling signal amplification, while a source resistor $ R_S $ (frequently bypassed by a capacitor $ C_S $ for AC coupling) may link the source to ground for stability. Gatebiasing components, such as a gateresistor $ R_G $ to ground or a bias voltage source, ensure the transistor operates in its active region; input and output couplingcapacitors $ C_{in} $ and $ C_{out} $ isolate DC while transmitting AC signals. The FET can be n-channel or p-channel, with connections adjusted accordingly for enhancement-mode MOSFETs or depletion-mode JFETs.[5][4]The common-source configuration for FETs is analogous to the common-emitter amplifier for bipolar junction transistors. It evolved with the development of FETs, including the practical JFET demonstrated in 1953 by Dacey and Ross, and the MOSFET invented in 1959 by Atalla and Kahng.[6][7] Proper biasing arrangements are crucial to establish the quiescent operating point for reliable amplification.[5]
Biasing Arrangements
Biasing in a common source amplifier serves to establish a stable DC operating point by setting the gate-source voltage VGS and drain-source voltage VDS such that the MOSFET operates in the saturation (active) region, ensuring linear amplification while avoiding cutoff or triode regions.[8] This quiescent bias point is critical for consistent performance across temperature and device variations.[9]One common method is voltage dividerbias, where two high-value resistors RG1 and RG2 form a divider from the supply VDD to ground, setting a fixed gate voltage VG=VDD⋅RG1+RG2RG2.[10] With the source grounded, VGS=VG, and the drain current ID follows from the MOSFET's transfer characteristic, typically ID≈21μnCoxLW(VGS−Vth)2(1+λVDS).[10] Additionally, ID=RDVDD−VDS, where RD is the drain resistor.[9] This approach offers good thermal and supply stability due to the fixed VG, but it requires more components and can lead to variations in VGS if resistor values are not precisely matched to the device.[8][10]Self-bias employs an unbypassed source resistor RS to provide negative feedback for enhanced stability.[9] Here, VS=IDRS, so VGS=VG−VS=VG−IDRS, with VG often zero for simplicity or set by a gate divider.[9] The drain current is given by ID=RDVDD−VDS.[9] The RS prevents thermal runaway by raising VS as ID increases with temperature, thereby reducing VGS and limiting current growth.[9] This method is simpler and uses fewer components than voltage divider bias, promoting single-supply operation, but the unbypassed RS introduces degeneration that lowers the small-signal gain.[9][10]Drain-feedback bias connects a resistor from drain to gate, establishing the bias through loop feedback.[8] Applying Kirchhoff's voltage law yields VDD=IDRD+VGS, solving for ID based on the device curve.[8] This configuration achieves thermal stability via the feedback mechanism, similar to self-bias, and minimizes component count for compact designs.