| 1 | // locks.h - Thread synchronization primitives. Sparc implementation.
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| 2 |
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| 3 | /* Copyright (C) 2002 Free Software Foundation
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| 4 |
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| 5 | This file is part of libgcj.
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| 6 |
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| 7 | This software is copyrighted work licensed under the terms of the
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| 8 | Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
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| 9 | details. */
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| 10 |
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| 11 | #ifndef __SYSDEP_LOCKS_H__
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| 12 | #define __SYSDEP_LOCKS_H__
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| 13 |
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| 14 | typedef size_t obj_addr_t; /* Integer type big enough for object */
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| 15 | /* address. */
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| 16 |
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| 17 | #ifdef __arch64__
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| 18 | /* Sparc64 implementation, use cas instruction. */
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| 19 | inline static bool
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| 20 | compare_and_swap(volatile obj_addr_t *addr,
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| 21 | obj_addr_t old,
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| 22 | obj_addr_t new_val)
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| 23 | {
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| 24 | __asm__ __volatile__("casx [%2], %3, %0\n\t"
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| 25 | "membar #StoreLoad | #StoreStore"
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| 26 | : "=&r" (new_val)
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| 27 | : "0" (new_val), "r" (addr), "r" (old)
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| 28 | : "memory");
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| 29 |
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| 30 | return (new_val == old) ? true : false;
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| 31 | }
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| 32 |
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| 33 | inline static void
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| 34 | release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
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| 35 | {
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| 36 | __asm__ __volatile__("membar #StoreStore | #LoadStore" : : : "memory");
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| 37 | *(addr) = new_val;
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| 38 | }
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| 39 |
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| 40 | inline static bool
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| 41 | compare_and_swap_release(volatile obj_addr_t *addr,
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| 42 | obj_addr_t old,
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| 43 | obj_addr_t new_val)
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| 44 | {
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| 45 | return compare_and_swap(addr, old, new_val);
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| 46 | }
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| 47 | #else
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| 48 | /* Sparc32 implementation, use a spinlock. */
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| 49 | static unsigned char __cas_lock = 0;
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| 50 |
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| 51 | inline static void
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| 52 | __cas_start_atomic(void)
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| 53 | {
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| 54 | unsigned int tmp;
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| 55 | __asm__ __volatile__(
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| 56 | "1: ldstub [%1], %0\n"
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| 57 | " orcc %0, 0x0, %g0\n"
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| 58 | " be 3f\n"
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| 59 | " nop\n"
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| 60 | "2: ldub [%1], %0\n"
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| 61 | " orcc %0, 0x0, %g0\n"
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| 62 | " bne 2b\n"
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| 63 | " nop\n"
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| 64 | "3:" : "=&r" (tmp)
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| 65 | : "r" (&__cas_lock)
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| 66 | : "memory", "cc");
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| 67 | }
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| 68 |
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| 69 | inline static void
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| 70 | __cas_end_atomic(void)
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| 71 | {
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| 72 | __asm__ __volatile__(
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| 73 | "stb %%g0, [%0]"
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| 74 | : /* no outputs */
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| 75 | : "r" (&__cas_lock)
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| 76 | : "memory");
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| 77 | }
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| 78 |
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| 79 | inline static bool
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| 80 | compare_and_swap(volatile obj_addr_t *addr,
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| 81 | obj_addr_t old,
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| 82 | obj_addr_t new_val)
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| 83 | {
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| 84 | bool ret;
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| 85 |
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| 86 | __cas_start_atomic ();
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| 87 | if (*addr != old)
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| 88 | {
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| 89 | ret = false;
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| 90 | }
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| 91 | else
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| 92 | {
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| 93 | *addr = new_val;
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| 94 | ret = true;
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| 95 | }
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| 96 | __cas_end_atomic ();
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| 97 |
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| 98 | return ret;
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| 99 | }
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| 100 |
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| 101 | inline static void
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| 102 | release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
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| 103 | {
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| 104 | /* Technically stbar would be needed here but no sparc32
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| 105 | system actually requires it. Also the stbar would mean
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| 106 | this code would not work on sparcv7 chips. */
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| 107 | __asm__ __volatile__("" : : : "memory");
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| 108 | *(addr) = new_val;
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| 109 | }
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| 110 |
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| 111 | inline static bool
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| 112 | compare_and_swap_release(volatile obj_addr_t *addr,
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| 113 | obj_addr_t old,
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| 114 | obj_addr_t new_val)
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| 115 | {
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| 116 | return compare_and_swap(addr, old, new_val);
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| 117 | }
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| 118 | #endif /* __arch64__ */
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| 119 |
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| 120 | #endif /* ! __SYSDEP_LOCKS_H__ */
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