| 1 | // locks.h - Thread synchronization primitives. PowerPC implementation.
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| 2 |
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| 3 | /* Copyright (C) 2002 Free Software Foundation
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| 4 |
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| 5 | This file is part of libgcj.
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| 6 |
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| 7 | This software is copyrighted work licensed under the terms of the
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| 8 | Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
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| 9 | details. */
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| 10 |
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| 11 | #ifndef __SYSDEP_LOCKS_H__
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| 12 | #define __SYSDEP_LOCKS_H__
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| 13 |
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| 14 | #ifdef __powerpc64__
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| 15 | #define _LARX "ldarx "
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| 16 | #define _STCX "stdcx. "
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| 17 | #else
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| 18 | #define _LARX "lwarx "
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| 19 | #ifdef __PPC405__
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| 20 | #define _STCX "sync; stwcx. "
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| 21 | #else
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| 22 | #define _STCX "stwcx. "
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| 23 | #endif
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| 24 | #endif
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| 25 |
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| 26 | typedef size_t obj_addr_t; /* Integer type big enough for object */
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| 27 | /* address. */
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| 28 |
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| 29 | inline static bool
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| 30 | compare_and_swap (volatile obj_addr_t *addr, obj_addr_t old,
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| 31 | obj_addr_t new_val)
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| 32 | {
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| 33 | int ret;
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| 34 |
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| 35 | __asm__ __volatile__ (
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| 36 | "0: " _LARX "%0,0,%1 ;"
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| 37 | " xor. %0,%3,%0;"
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| 38 | " bne 1f;"
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| 39 | " " _STCX "%2,0,%1;"
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| 40 | " bne- 0b;"
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| 41 | "1: "
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| 42 | : "=&r" (ret)
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| 43 | : "r" (addr), "r" (new_val), "r" (old)
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| 44 | : "cr0", "memory");
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| 45 |
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| 46 | /* This version of __compare_and_swap is to be used when acquiring
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| 47 | a lock, so we don't need to worry about whether other memory
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| 48 | operations have completed, but we do need to be sure that any loads
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| 49 | after this point really occur after we have acquired the lock. */
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| 50 | __asm__ __volatile__ ("isync" : : : "memory");
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| 51 | return ret == 0;
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| 52 | }
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| 53 |
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| 54 | inline static void
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| 55 | release_set (volatile obj_addr_t *addr, obj_addr_t new_val)
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| 56 | {
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| 57 | __asm__ __volatile__ ("sync" : : : "memory");
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| 58 | *addr = new_val;
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| 59 | }
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| 60 |
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| 61 | inline static bool
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| 62 | compare_and_swap_release (volatile obj_addr_t *addr, obj_addr_t old,
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| 63 | obj_addr_t new_val)
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| 64 | {
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| 65 | int ret;
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| 66 |
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| 67 | __asm__ __volatile__ ("sync" : : : "memory");
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| 68 |
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| 69 | __asm__ __volatile__ (
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| 70 | "0: " _LARX "%0,0,%1 ;"
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| 71 | " xor. %0,%3,%0;"
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| 72 | " bne 1f;"
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| 73 | " " _STCX "%2,0,%1;"
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| 74 | " bne- 0b;"
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| 75 | "1: "
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| 76 | : "=&r" (ret)
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| 77 | : "r" (addr), "r" (new_val), "r" (old)
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| 78 | : "cr0", "memory");
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| 79 |
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| 80 | return ret == 0;
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| 81 | }
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| 82 |
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| 83 | // Ensure that subsequent instructions do not execute on stale
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| 84 | // data that was loaded from memory before the barrier.
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| 85 | inline static void
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| 86 | read_barrier ()
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| 87 | {
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| 88 | __asm__ __volatile__ ("isync" : : : "memory");
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| 89 | }
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| 90 |
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| 91 | // Ensure that prior stores to memory are completed with respect to other
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| 92 | // processors.
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| 93 | inline static void
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| 94 | write_barrier ()
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| 95 | {
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| 96 | __asm__ __volatile__ ("sync" : : : "memory");
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| 97 | }
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| 98 |
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| 99 | #endif
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