| 1 | /* Assembler instructions for Motorola's Mcore processor
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| 2 | Copyright 1999, 2000 Free Software Foundation, Inc.
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| 3 |
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| 4 |
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| 5 | This program is free software; you can redistribute it and/or modify
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| 6 | it under the terms of the GNU General Public License as published by
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| 7 | the Free Software Foundation; either version 2 of the License, or
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| 8 | (at your option) any later version.
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| 9 |
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| 10 | This program is distributed in the hope that it will be useful,
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| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 13 | GNU General Public License for more details.
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| 14 |
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| 15 | You should have received a copy of the GNU General Public License
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| 16 | along with this program; if not, write to the Free Software
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| 17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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| 18 |
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| 19 | #include "ansidecl.h"
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| 20 |
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| 21 | typedef enum
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| 22 | {
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| 23 | O0, OT, O1, OC, O2, X1, OI, OB,
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| 24 | OMa, SI, I7, LS, BR, BL, LR, LJ,
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| 25 | RM, RQ, JSR, JMP, OBRa, OBRb, OBRc, OBR2,
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| 26 | O1R1, OMb, OMc, SIa,
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| 27 | MULSH, OPSR,
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| 28 | JC, JU, JL, RSI, DO21, OB2
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| 29 | }
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| 30 | mcore_opclass;
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| 31 |
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| 32 | typedef struct inst
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| 33 | {
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| 34 | char * name;
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| 35 | mcore_opclass opclass;
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| 36 | unsigned char transfer;
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| 37 | unsigned short inst;
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| 38 | }
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| 39 | mcore_opcode_info;
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| 40 |
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| 41 | #ifdef DEFINE_TABLE
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| 42 | mcore_opcode_info mcore_table[] =
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| 43 | {
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| 44 | { "bkpt", O0, 0, 0x0000 },
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| 45 | { "sync", O0, 0, 0x0001 },
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| 46 | { "rte", O0, 1, 0x0002 },
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| 47 | { "rfe", O0, 1, 0x0002 },
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| 48 | { "rfi", O0, 1, 0x0003 },
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| 49 | { "stop", O0, 0, 0x0004 },
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| 50 | { "wait", O0, 0, 0x0005 },
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| 51 | { "doze", O0, 0, 0x0006 },
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| 52 | { "idly4", O0, 0, 0x0007 },
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| 53 | { "trap", OT, 0, 0x0008 },
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| 54 | /* SPACE: 0x000C - 0x000F */
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| 55 | /* SPACE: 0x0010 - 0x001F */
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| 56 | { "mvc", O1, 0, 0x0020 },
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| 57 | { "mvcv", O1, 0, 0x0030 },
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| 58 | { "ldq", RQ, 0, 0x0040 },
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| 59 | { "stq", RQ, 0, 0x0050 },
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| 60 | { "ldm", RM, 0, 0x0060 },
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| 61 | { "stm", RM, 0, 0x0070 },
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| 62 | { "dect", O1, 0, 0x0080 },
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| 63 | { "decf", O1, 0, 0x0090 },
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| 64 | { "inct", O1, 0, 0x00A0 },
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| 65 | { "incf", O1, 0, 0x00B0 },
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| 66 | { "jmp", JMP, 2, 0x00C0 },
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| 67 | #define MCORE_INST_JMP 0x00C0
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| 68 | { "jsr", JSR, 0, 0x00D0 },
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| 69 | #define MCORE_INST_JSR 0x00E0
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| 70 | { "ff1", O1, 0, 0x00E0 },
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| 71 | { "brev", O1, 0, 0x00F0 },
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| 72 | { "xtrb3", X1, 0, 0x0100 },
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| 73 | { "xtrb2", X1, 0, 0x0110 },
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| 74 | { "xtrb1", X1, 0, 0x0120 },
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| 75 | { "xtrb0", X1, 0, 0x0130 },
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| 76 | { "zextb", O1, 0, 0x0140 },
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| 77 | { "sextb", O1, 0, 0x0150 },
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| 78 | { "zexth", O1, 0, 0x0160 },
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| 79 | { "sexth", O1, 0, 0x0170 },
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| 80 | { "declt", O1, 0, 0x0180 },
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| 81 | { "tstnbz", O1, 0, 0x0190 },
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| 82 | { "decgt", O1, 0, 0x01A0 },
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| 83 | { "decne", O1, 0, 0x01B0 },
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| 84 | { "clrt", O1, 0, 0x01C0 },
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| 85 | { "clrf", O1, 0, 0x01D0 },
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| 86 | { "abs", O1, 0, 0x01E0 },
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| 87 | { "not", O1, 0, 0x01F0 },
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| 88 | { "movt", O2, 0, 0x0200 },
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| 89 | { "mult", O2, 0, 0x0300 },
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| 90 | { "loopt", BL, 0, 0x0400 },
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| 91 | { "subu", O2, 0, 0x0500 },
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| 92 | { "sub", O2, 0, 0x0500 }, /* Official alias. */
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| 93 | { "addc", O2, 0, 0x0600 },
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| 94 | { "subc", O2, 0, 0x0700 },
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| 95 | /* SPACE: 0x0800-0x08ff for a diadic operation */
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| 96 | /* SPACE: 0x0900-0x09ff for a diadic operation */
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| 97 | { "movf", O2, 0, 0x0A00 },
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| 98 | { "lsr", O2, 0, 0x0B00 },
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| 99 | { "cmphs", O2, 0, 0x0C00 },
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| 100 | { "cmplt", O2, 0, 0x0D00 },
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| 101 | { "tst", O2, 0, 0x0E00 },
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| 102 | { "cmpne", O2, 0, 0x0F00 },
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| 103 | { "mfcr", OC, 0, 0x1000 },
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| 104 | { "psrclr", OPSR, 0, 0x11F0 },
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| 105 | { "psrset", OPSR, 0, 0x11F8 },
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| 106 | { "mov", O2, 0, 0x1200 },
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| 107 | { "bgenr", O2, 0, 0x1300 },
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| 108 | { "rsub", O2, 0, 0x1400 },
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| 109 | { "ixw", O2, 0, 0x1500 },
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| 110 | { "and", O2, 0, 0x1600 },
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| 111 | { "xor", O2, 0, 0x1700 },
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| 112 | { "mtcr", OC, 0, 0x1800 },
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| 113 | { "asr", O2, 0, 0x1A00 },
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| 114 | { "lsl", O2, 0, 0x1B00 },
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| 115 | { "addu", O2, 0, 0x1C00 },
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| 116 | { "add", O2, 0, 0x1C00 }, /* Official alias. */
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| 117 | { "ixh", O2, 0, 0x1D00 },
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| 118 | { "or", O2, 0, 0x1E00 },
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| 119 | { "andn", O2, 0, 0x1F00 },
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| 120 | { "addi", OI, 0, 0x2000 },
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| 121 | #define MCORE_INST_ADDI 0x2000
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| 122 | { "cmplti", OI, 0, 0x2200 },
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| 123 | { "subi", OI, 0, 0x2400 },
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| 124 | /* SPACE: 0x2600-0x27ff open for a register+immediate operation */
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| 125 | { "rsubi", OB, 0, 0x2800 },
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| 126 | { "cmpnei", OB, 0, 0x2A00 },
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| 127 | { "bmaski", OMa, 0, 0x2C00 },
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| 128 | { "divu", O1R1, 0, 0x2C10 },
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| 129 | /* SPACE: 0x2c20 - 0x2c7f */
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| 130 | { "bmaski", OMb, 0, 0x2C80 },
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| 131 | { "bmaski", OMc, 0, 0x2D00 },
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| 132 | { "andi", OB, 0, 0x2E00 },
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| 133 | { "bclri", OB, 0, 0x3000 },
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| 134 | /* SPACE: 0x3200 - 0x320f */
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| 135 | { "divs", O1R1, 0, 0x3210 },
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| 136 | /* SPACE: 0x3220 - 0x326f */
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| 137 | { "bgeni", OBRa, 0, 0x3270 },
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| 138 | { "bgeni", OBRb, 0, 0x3280 },
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| 139 | { "bgeni", OBRc, 0, 0x3300 },
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| 140 | { "bseti", OB, 0, 0x3400 },
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| 141 | { "btsti", OB, 0, 0x3600 },
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| 142 | { "xsr", O1, 0, 0x3800 },
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| 143 | { "rotli", SIa, 0, 0x3800 },
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| 144 | { "asrc", O1, 0, 0x3A00 },
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| 145 | { "asri", SIa, 0, 0x3A00 },
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| 146 | { "lslc", O1, 0, 0x3C00 },
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| 147 | { "lsli", SIa, 0, 0x3C00 },
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| 148 | { "lsrc", O1, 0, 0x3E00 },
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| 149 | { "lsri", SIa, 0, 0x3E00 },
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| 150 | /* SPACE: 0x4000 - 0x5fff */
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| 151 | { "movi", I7, 0, 0x6000 },
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| 152 | #define MCORE_INST_BMASKI_ALT 0x6000
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| 153 | #define MCORE_INST_BGENI_ALT 0x6000
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| 154 | { "mulsh", MULSH, 0, 0x6800 },
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| 155 | { "muls.h", MULSH, 0, 0x6800 },
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| 156 | /* SPACE: 0x6900 - 0x6FFF */
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| 157 | { "jmpi", LJ, 1, 0x7000 },
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| 158 | { "jsri", LJ, 0, 0x7F00 },
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| 159 | #define MCORE_INST_JMPI 0x7000
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| 160 | { "lrw", LR, 0, 0x7000 },
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| 161 | #define MCORE_INST_JSRI 0x7F00
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| 162 | { "ld", LS, 0, 0x8000 },
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| 163 | { "ldw", LS, 0, 0x8000 },
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| 164 | { "ld.w", LS, 0, 0x8000 },
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| 165 | { "st", LS, 0, 0x9000 },
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| 166 | { "stw", LS, 0, 0x9000 },
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| 167 | { "st.w", LS, 0, 0x9000 },
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| 168 | { "ldb", LS, 0, 0xA000 },
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| 169 | { "ld.b", LS, 0, 0xA000 },
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| 170 | { "stb", LS, 0, 0xB000 },
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| 171 | { "st.b", LS, 0, 0xB000 },
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| 172 | { "ldh", LS, 0, 0xC000 },
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| 173 | { "ld.h", LS, 0, 0xC000 },
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| 174 | { "sth", LS, 0, 0xD000 },
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| 175 | { "st.h", LS, 0, 0xD000 },
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| 176 | { "bt", BR, 0, 0xE000 },
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| 177 | { "bf", BR, 0, 0xE800 },
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| 178 | { "br", BR, 1, 0xF000 },
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| 179 | #define MCORE_INST_BR 0xF000
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| 180 | { "bsr", BR, 0, 0xF800 },
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| 181 | #define MCORE_INST_BSR 0xF800
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| 182 |
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| 183 | /* The following are relaxable branches */
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| 184 | { "jbt", JC, 0, 0xE000 },
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| 185 | { "jbf", JC, 0, 0xE800 },
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| 186 | { "jbr", JU, 1, 0xF000 },
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| 187 | { "jbsr", JL, 0, 0xF800 },
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| 188 |
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| 189 | /* The following are aliases for other instructions */
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| 190 | { "rts", O0, 2, 0x00CF }, /* jmp r15 */
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| 191 | { "rolc", DO21, 0, 0x0600 }, /* addc rd,rd */
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| 192 | { "rotlc", DO21, 0, 0x0600 }, /* addc rd,rd */
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| 193 | { "setc", O0, 0, 0x0C00 }, /* cmphs r0,r0 */
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| 194 | { "clrc", O0, 0, 0x0F00 }, /* cmpne r0,r0 */
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| 195 | { "tstle", O1, 0, 0x2200 }, /* cmplti rd,1 */
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| 196 | { "cmplei", OB, 0, 0x2200 }, /* cmplei rd,X -> cmplti rd,X+1 */
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| 197 | { "neg", O1, 0, 0x2800 }, /* rsubi rd,0 */
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| 198 | { "tstne", O1, 0, 0x2A00 }, /* cmpnei rd,0 */
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| 199 | { "tstlt", O1, 0, 0x37F0 }, /* btsti rx,31 */
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| 200 | { "mclri", OB2, 0, 0x3000 }, /* bclri rx,log2(imm) */
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| 201 | { "mgeni", OBR2, 0, 0x3200 }, /* bgeni rx,log2(imm) */
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| 202 | { "mseti", OB2, 0, 0x3400 }, /* bseti rx,log2(imm) */
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| 203 | { "mtsti", OB2, 0, 0x3600 }, /* btsti rx,log2(imm) */
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| 204 | { "rori", RSI, 0, 0x3800 },
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| 205 | { "rotri", RSI, 0, 0x3800 },
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| 206 | { "nop", O0, 0, 0x1200 }, /* mov r0, r0 */
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| 207 | { 0, 0, 0, 0 }
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| 208 | };
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| 209 | #endif
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