| 1 | /* mips.h. Mips opcode list for GDB, the GNU debugger.
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| 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
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| 3 | Free Software Foundation, Inc.
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| 4 | Contributed by Ralph Campbell and OSF
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| 5 | Commented and modified by Ian Lance Taylor, Cygnus Support
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| 6 |
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| 7 | This file is part of GDB, GAS, and the GNU binutils.
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| 8 |
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| 9 | GDB, GAS, and the GNU binutils are free software; you can redistribute
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| 10 | them and/or modify them under the terms of the GNU General Public
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| 11 | License as published by the Free Software Foundation; either version
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| 12 | 1, or (at your option) any later version.
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| 13 |
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| 14 | GDB, GAS, and the GNU binutils are distributed in the hope that they
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| 15 | will be useful, but WITHOUT ANY WARRANTY; without even the implied
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| 16 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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| 17 | the GNU General Public License for more details.
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| 18 |
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| 19 | You should have received a copy of the GNU General Public License
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| 20 | along with this file; see the file COPYING. If not, write to the Free
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| 21 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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| 22 |
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| 23 | #ifndef _MIPS_H_
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| 24 | #define _MIPS_H_
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| 25 |
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| 26 | /* These are bit masks and shift counts to use to access the various
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| 27 | fields of an instruction. To retrieve the X field of an
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| 28 | instruction, use the expression
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| 29 | (i >> OP_SH_X) & OP_MASK_X
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| 30 | To set the same field (to j), use
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| 31 | i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
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| 32 |
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| 33 | Make sure you use fields that are appropriate for the instruction,
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| 34 | of course.
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| 35 |
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| 36 | The 'i' format uses OP, RS, RT and IMMEDIATE.
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| 37 |
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| 38 | The 'j' format uses OP and TARGET.
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| 39 |
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| 40 | The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
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| 41 |
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| 42 | The 'b' format uses OP, RS, RT and DELTA.
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| 43 |
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| 44 | The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
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| 45 |
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| 46 | The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
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| 47 |
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| 48 | A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
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| 49 | breakpoint instruction are not defined; Kane says the breakpoint
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| 50 | code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
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| 51 | only use ten bits). An optional two-operand form of break/sdbbp
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| 52 | allows the lower ten bits to be set too, and MIPS32 and later
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| 53 | architectures allow 20 bits to be set with a signal operand
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| 54 | (using CODE20).
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| 55 |
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| 56 | The syscall instruction uses CODE20.
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| 57 |
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| 58 | The general coprocessor instructions use COPZ. */
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| 59 |
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| 60 | #define OP_MASK_OP 0x3f
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| 61 | #define OP_SH_OP 26
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| 62 | #define OP_MASK_RS 0x1f
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| 63 | #define OP_SH_RS 21
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| 64 | #define OP_MASK_FR 0x1f
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| 65 | #define OP_SH_FR 21
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| 66 | #define OP_MASK_FMT 0x1f
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| 67 | #define OP_SH_FMT 21
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| 68 | #define OP_MASK_BCC 0x7
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| 69 | #define OP_SH_BCC 18
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| 70 | #define OP_MASK_CODE 0x3ff
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| 71 | #define OP_SH_CODE 16
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| 72 | #define OP_MASK_CODE2 0x3ff
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| 73 | #define OP_SH_CODE2 6
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| 74 | #define OP_MASK_RT 0x1f
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| 75 | #define OP_SH_RT 16
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| 76 | #define OP_MASK_FT 0x1f
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| 77 | #define OP_SH_FT 16
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| 78 | #define OP_MASK_CACHE 0x1f
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| 79 | #define OP_SH_CACHE 16
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| 80 | #define OP_MASK_RD 0x1f
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| 81 | #define OP_SH_RD 11
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| 82 | #define OP_MASK_FS 0x1f
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| 83 | #define OP_SH_FS 11
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| 84 | #define OP_MASK_PREFX 0x1f
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| 85 | #define OP_SH_PREFX 11
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| 86 | #define OP_MASK_CCC 0x7
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| 87 | #define OP_SH_CCC 8
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| 88 | #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
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| 89 | #define OP_SH_CODE20 6
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| 90 | #define OP_MASK_SHAMT 0x1f
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| 91 | #define OP_SH_SHAMT 6
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| 92 | #define OP_MASK_FD 0x1f
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| 93 | #define OP_SH_FD 6
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| 94 | #define OP_MASK_TARGET 0x3ffffff
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| 95 | #define OP_SH_TARGET 0
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| 96 | #define OP_MASK_COPZ 0x1ffffff
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| 97 | #define OP_SH_COPZ 0
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| 98 | #define OP_MASK_IMMEDIATE 0xffff
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| 99 | #define OP_SH_IMMEDIATE 0
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| 100 | #define OP_MASK_DELTA 0xffff
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| 101 | #define OP_SH_DELTA 0
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| 102 | #define OP_MASK_FUNCT 0x3f
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| 103 | #define OP_SH_FUNCT 0
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| 104 | #define OP_MASK_SPEC 0x3f
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| 105 | #define OP_SH_SPEC 0
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| 106 | #define OP_SH_LOCC 8 /* FP condition code. */
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| 107 | #define OP_SH_HICC 18 /* FP condition code. */
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| 108 | #define OP_MASK_CC 0x7
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| 109 | #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
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| 110 | #define OP_MASK_COP1NORM 0x1 /* a single bit. */
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| 111 | #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
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| 112 | #define OP_MASK_COP1SPEC 0xf
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| 113 | #define OP_MASK_COP1SCLR 0x4
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| 114 | #define OP_MASK_COP1CMP 0x3
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| 115 | #define OP_SH_COP1CMP 4
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| 116 | #define OP_SH_FORMAT 21 /* FP short format field. */
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| 117 | #define OP_MASK_FORMAT 0x7
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| 118 | #define OP_SH_TRUE 16
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| 119 | #define OP_MASK_TRUE 0x1
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| 120 | #define OP_SH_GE 17
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| 121 | #define OP_MASK_GE 0x01
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| 122 | #define OP_SH_UNSIGNED 16
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| 123 | #define OP_MASK_UNSIGNED 0x1
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| 124 | #define OP_SH_HINT 16
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| 125 | #define OP_MASK_HINT 0x1f
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| 126 | #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
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| 127 | #define OP_MASK_MMI 0x3f
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| 128 | #define OP_SH_MMISUB 6
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| 129 | #define OP_MASK_MMISUB 0x1f
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| 130 | #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
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| 131 | #define OP_SH_PERFREG 1
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| 132 | #define OP_SH_SEL 0 /* Coprocessor select field. */
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| 133 | #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
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| 134 | #define OP_SH_CODE19 6 /* 19 bit wait code. */
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| 135 | #define OP_MASK_CODE19 0x7ffff
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| 136 |
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| 137 | /* This structure holds information for a particular instruction. */
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| 138 |
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| 139 | struct mips_opcode
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| 140 | {
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| 141 | /* The name of the instruction. */
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| 142 | const char *name;
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| 143 | /* A string describing the arguments for this instruction. */
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| 144 | const char *args;
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| 145 | /* The basic opcode for the instruction. When assembling, this
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| 146 | opcode is modified by the arguments to produce the actual opcode
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| 147 | that is used. If pinfo is INSN_MACRO, then this is 0. */
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| 148 | unsigned long match;
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| 149 | /* If pinfo is not INSN_MACRO, then this is a bit mask for the
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| 150 | relevant portions of the opcode when disassembling. If the
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| 151 | actual opcode anded with the match field equals the opcode field,
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| 152 | then we have found the correct instruction. If pinfo is
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| 153 | INSN_MACRO, then this field is the macro identifier. */
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| 154 | unsigned long mask;
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| 155 | /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
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| 156 | of bits describing the instruction, notably any relevant hazard
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| 157 | information. */
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| 158 | unsigned long pinfo;
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| 159 | /* A collection of bits describing the instruction sets of which this
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| 160 | instruction or macro is a member. */
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| 161 | unsigned long membership;
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| 162 | };
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| 163 |
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| 164 | /* These are the characters which may appears in the args field of an
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| 165 | instruction. They appear in the order in which the fields appear
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| 166 | when the instruction is used. Commas and parentheses in the args
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| 167 | string are ignored when assembling, and written into the output
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| 168 | when disassembling.
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| 169 |
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| 170 | Each of these characters corresponds to a mask field defined above.
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| 171 |
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| 172 | "<" 5 bit shift amount (OP_*_SHAMT)
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| 173 | ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
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| 174 | "a" 26 bit target address (OP_*_TARGET)
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| 175 | "b" 5 bit base register (OP_*_RS)
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| 176 | "c" 10 bit breakpoint code (OP_*_CODE)
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| 177 | "d" 5 bit destination register specifier (OP_*_RD)
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| 178 | "h" 5 bit prefx hint (OP_*_PREFX)
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| 179 | "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
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| 180 | "j" 16 bit signed immediate (OP_*_DELTA)
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| 181 | "k" 5 bit cache opcode in target register position (OP_*_CACHE)
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| 182 | "o" 16 bit signed offset (OP_*_DELTA)
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| 183 | "p" 16 bit PC relative branch target address (OP_*_DELTA)
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| 184 | "q" 10 bit extra breakpoint code (OP_*_CODE2)
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| 185 | "r" 5 bit same register used as both source and target (OP_*_RS)
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| 186 | "s" 5 bit source register specifier (OP_*_RS)
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| 187 | "t" 5 bit target register (OP_*_RT)
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| 188 | "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
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| 189 | "v" 5 bit same register used as both source and destination (OP_*_RS)
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| 190 | "w" 5 bit same register used as both target and destination (OP_*_RT)
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| 191 | "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
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| 192 | (used by clo and clz)
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| 193 | "C" 25 bit coprocessor function code (OP_*_COPZ)
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| 194 | "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
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| 195 | "J" 19 bit wait function code (OP_*_CODE19)
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| 196 | "x" accept and ignore register name
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| 197 | "z" must be zero register
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| 198 |
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| 199 | Floating point instructions:
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| 200 | "D" 5 bit destination register (OP_*_FD)
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| 201 | "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
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| 202 | "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
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| 203 | "S" 5 bit fs source 1 register (OP_*_FS)
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| 204 | "T" 5 bit ft source 2 register (OP_*_FT)
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| 205 | "R" 5 bit fr source 3 register (OP_*_FR)
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| 206 | "V" 5 bit same register used as floating source and destination (OP_*_FS)
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| 207 | "W" 5 bit same register used as floating target and destination (OP_*_FT)
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| 208 |
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| 209 | Coprocessor instructions:
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| 210 | "E" 5 bit target register (OP_*_RT)
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| 211 | "G" 5 bit destination register (OP_*_RD)
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| 212 | "P" 5 bit performance-monitor register (OP_*_PERFREG)
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| 213 | "H" 3 bit sel field (OP_*_SEL)
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| 214 |
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| 215 | Macro instructions:
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| 216 | "A" General 32 bit expression
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| 217 | "I" 32 bit immediate
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| 218 | "F" 64 bit floating point constant in .rdata
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| 219 | "L" 64 bit floating point constant in .lit8
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| 220 | "f" 32 bit floating point constant
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| 221 | "l" 32 bit floating point constant in .lit4
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| 222 |
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| 223 | Other:
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| 224 | "()" parens surrounding optional value
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| 225 | "," separates operands
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| 226 |
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| 227 | Characters used so far, for quick reference when adding more:
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| 228 | "<>(),"
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| 229 | "ABCDEFGHIJLMNPRSTUVW"
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| 230 | "abcdfhijklopqrstuvwxz"
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| 231 | */
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| 232 |
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| 233 | /* These are the bits which may be set in the pinfo field of an
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| 234 | instructions, if it is not equal to INSN_MACRO. */
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| 235 |
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| 236 | /* Modifies the general purpose register in OP_*_RD. */
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| 237 | #define INSN_WRITE_GPR_D 0x00000001
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| 238 | /* Modifies the general purpose register in OP_*_RT. */
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| 239 | #define INSN_WRITE_GPR_T 0x00000002
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| 240 | /* Modifies general purpose register 31. */
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| 241 | #define INSN_WRITE_GPR_31 0x00000004
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| 242 | /* Modifies the floating point register in OP_*_FD. */
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| 243 | #define INSN_WRITE_FPR_D 0x00000008
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| 244 | /* Modifies the floating point register in OP_*_FS. */
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| 245 | #define INSN_WRITE_FPR_S 0x00000010
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| 246 | /* Modifies the floating point register in OP_*_FT. */
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| 247 | #define INSN_WRITE_FPR_T 0x00000020
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| 248 | /* Reads the general purpose register in OP_*_RS. */
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| 249 | #define INSN_READ_GPR_S 0x00000040
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| 250 | /* Reads the general purpose register in OP_*_RT. */
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| 251 | #define INSN_READ_GPR_T 0x00000080
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| 252 | /* Reads the floating point register in OP_*_FS. */
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| 253 | #define INSN_READ_FPR_S 0x00000100
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| 254 | /* Reads the floating point register in OP_*_FT. */
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| 255 | #define INSN_READ_FPR_T 0x00000200
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| 256 | /* Reads the floating point register in OP_*_FR. */
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| 257 | #define INSN_READ_FPR_R 0x00000400
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| 258 | /* Modifies coprocessor condition code. */
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| 259 | #define INSN_WRITE_COND_CODE 0x00000800
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| 260 | /* Reads coprocessor condition code. */
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| 261 | #define INSN_READ_COND_CODE 0x00001000
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| 262 | /* TLB operation. */
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| 263 | #define INSN_TLB 0x00002000
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| 264 | /* Reads coprocessor register other than floating point register. */
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| 265 | #define INSN_COP 0x00004000
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| 266 | /* Instruction loads value from memory, requiring delay. */
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| 267 | #define INSN_LOAD_MEMORY_DELAY 0x00008000
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| 268 | /* Instruction loads value from coprocessor, requiring delay. */
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| 269 | #define INSN_LOAD_COPROC_DELAY 0x00010000
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| 270 | /* Instruction has unconditional branch delay slot. */
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| 271 | #define INSN_UNCOND_BRANCH_DELAY 0x00020000
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| 272 | /* Instruction has conditional branch delay slot. */
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| 273 | #define INSN_COND_BRANCH_DELAY 0x00040000
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| 274 | /* Conditional branch likely: if branch not taken, insn nullified. */
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| 275 | #define INSN_COND_BRANCH_LIKELY 0x00080000
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| 276 | /* Moves to coprocessor register, requiring delay. */
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| 277 | #define INSN_COPROC_MOVE_DELAY 0x00100000
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| 278 | /* Loads coprocessor register from memory, requiring delay. */
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| 279 | #define INSN_COPROC_MEMORY_DELAY 0x00200000
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| 280 | /* Reads the HI register. */
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| 281 | #define INSN_READ_HI 0x00400000
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| 282 | /* Reads the LO register. */
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| 283 | #define INSN_READ_LO 0x00800000
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| 284 | /* Modifies the HI register. */
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| 285 | #define INSN_WRITE_HI 0x01000000
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| 286 | /* Modifies the LO register. */
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| 287 | #define INSN_WRITE_LO 0x02000000
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| 288 | /* Takes a trap (easier to keep out of delay slot). */
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| 289 | #define INSN_TRAP 0x04000000
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| 290 | /* Instruction stores value into memory. */
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| 291 | #define INSN_STORE_MEMORY 0x08000000
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| 292 | /* Instruction uses single precision floating point. */
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| 293 | #define FP_S 0x10000000
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| 294 | /* Instruction uses double precision floating point. */
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| 295 | #define FP_D 0x20000000
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| 296 | /* Instruction is part of the tx39's integer multiply family. */
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| 297 | #define INSN_MULT 0x40000000
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| 298 | /* Instruction synchronize shared memory. */
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| 299 | #define INSN_SYNC 0x80000000
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| 300 |
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| 301 | /* Instruction is actually a macro. It should be ignored by the
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| 302 | disassembler, and requires special treatment by the assembler. */
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| 303 | #define INSN_MACRO 0xffffffff
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| 304 |
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| 305 | /* Masks used to mark instructions to indicate which MIPS ISA level
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| 306 | they were introduced in. ISAs, as defined below, are logical
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| 307 | ORs of these bits, indicatingthat they support the instructions
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| 308 | defined at the given level. */
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| 309 |
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| 310 | #define INSN_ISA_MASK 0x0000ffff
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| 311 | #define INSN_ISA1 0x00000010
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| 312 | #define INSN_ISA2 0x00000020
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| 313 | #define INSN_ISA3 0x00000040
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| 314 | #define INSN_ISA4 0x00000080
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| 315 | #define INSN_ISA5 0x00000100
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| 316 | #define INSN_ISA32 0x00000200
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| 317 | #define INSN_ISA64 0x00000400
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| 318 |
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| 319 | /* Chip specific instructions. These are bitmasks. */
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| 320 |
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| 321 | /* MIPS R4650 instruction. */
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| 322 | #define INSN_4650 0x00010000
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| 323 | /* LSI R4010 instruction. */
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| 324 | #define INSN_4010 0x00020000
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| 325 | /* NEC VR4100 instruction. */
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| 326 | #define INSN_4100 0x00040000
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| 327 | /* Toshiba R3900 instruction. */
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| 328 | #define INSN_3900 0x00080000
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| 329 | /* 32-bit code running on a ISA3+ CPU. */
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| 330 | #define INSN_GP32 0x00100000
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| 331 |
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| 332 | /* MIPS ISA defines, use instead of hardcoding ISA level. */
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| 333 |
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| 334 | #define ISA_UNKNOWN 0 /* Gas internal use. */
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| 335 | #define ISA_MIPS1 (INSN_ISA1)
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| 336 | #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
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| 337 | #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
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| 338 | #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
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| 339 | #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
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| 340 | #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
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| 341 | #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
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| 342 |
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| 343 | /* CPU defines, use instead of hardcoding processor number. Keep this
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| 344 | in sync with bfd/archures.c in order for machine selection to work. */
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| 345 | #define CPU_UNKNOWN 0 /* Gas internal use. */
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| 346 | #define CPU_R2000 2000
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| 347 | #define CPU_R3000 3000
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| 348 | #define CPU_R3900 3900
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| 349 | #define CPU_R4000 4000
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| 350 | #define CPU_R4010 4010
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| 351 | #define CPU_VR4100 4100
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| 352 | #define CPU_R4111 4111
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| 353 | #define CPU_R4300 4300
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| 354 | #define CPU_R4400 4400
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| 355 | #define CPU_R4600 4600
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|---|
| 356 | #define CPU_R4650 4650
|
|---|
| 357 | #define CPU_R5000 5000
|
|---|
| 358 | #define CPU_R6000 6000
|
|---|
| 359 | #define CPU_R8000 8000
|
|---|
| 360 | #define CPU_R10000 10000
|
|---|
| 361 | #define CPU_R12000 12000
|
|---|
| 362 | #define CPU_MIPS16 16
|
|---|
| 363 | #define CPU_MIPS32 32
|
|---|
| 364 | #define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K'. */
|
|---|
| 365 | #define CPU_MIPS5 5
|
|---|
| 366 | #define CPU_MIPS64 64
|
|---|
| 367 | #define CPU_SB1 12310201 /* octal 'SB', 01. */
|
|---|
| 368 |
|
|---|
| 369 | /* Test for membership in an ISA including chip specific ISAs.
|
|---|
| 370 | INSN is pointer to an element of the opcode table; ISA is the
|
|---|
| 371 | specified ISA to test against; and CPU is the CPU specific ISA
|
|---|
| 372 | to test, or zero if no CPU specific ISA test is desired.
|
|---|
| 373 | The gp32 arg is set when you need to force 32-bit register usage on
|
|---|
| 374 | a machine with 64-bit registers; see the documentation under -mgp32
|
|---|
| 375 | in the MIPS gas docs. */
|
|---|
| 376 |
|
|---|
| 377 | #define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \
|
|---|
| 378 | ((((insn)->membership & isa) != 0 \
|
|---|
| 379 | && ((insn)->membership & INSN_GP32 ? gp32 : 1) \
|
|---|
| 380 | ) \
|
|---|
| 381 | || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
|
|---|
| 382 | || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|
|---|
| 383 | || ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
|
|---|
| 384 | && ((insn)->membership & INSN_4100) != 0) \
|
|---|
| 385 | || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0))
|
|---|
| 386 |
|
|---|
| 387 | /* This is a list of macro expanded instructions.
|
|---|
| 388 |
|
|---|
| 389 | _I appended means immediate
|
|---|
| 390 | _A appended means address
|
|---|
| 391 | _AB appended means address with base register
|
|---|
| 392 | _D appended means 64 bit floating point constant
|
|---|
| 393 | _S appended means 32 bit floating point constant. */
|
|---|
| 394 |
|
|---|
| 395 | enum
|
|---|
| 396 | {
|
|---|
| 397 | M_ABS,
|
|---|
| 398 | M_ADD_I,
|
|---|
| 399 | M_ADDU_I,
|
|---|
| 400 | M_AND_I,
|
|---|
| 401 | M_BEQ,
|
|---|
| 402 | M_BEQ_I,
|
|---|
| 403 | M_BEQL_I,
|
|---|
| 404 | M_BGE,
|
|---|
| 405 | M_BGEL,
|
|---|
| 406 | M_BGE_I,
|
|---|
| 407 | M_BGEL_I,
|
|---|
| 408 | M_BGEU,
|
|---|
| 409 | M_BGEUL,
|
|---|
| 410 | M_BGEU_I,
|
|---|
| 411 | M_BGEUL_I,
|
|---|
| 412 | M_BGT,
|
|---|
| 413 | M_BGTL,
|
|---|
| 414 | M_BGT_I,
|
|---|
| 415 | M_BGTL_I,
|
|---|
| 416 | M_BGTU,
|
|---|
| 417 | M_BGTUL,
|
|---|
| 418 | M_BGTU_I,
|
|---|
| 419 | M_BGTUL_I,
|
|---|
| 420 | M_BLE,
|
|---|
| 421 | M_BLEL,
|
|---|
| 422 | M_BLE_I,
|
|---|
| 423 | M_BLEL_I,
|
|---|
| 424 | M_BLEU,
|
|---|
| 425 | M_BLEUL,
|
|---|
| 426 | M_BLEU_I,
|
|---|
| 427 | M_BLEUL_I,
|
|---|
| 428 | M_BLT,
|
|---|
| 429 | M_BLTL,
|
|---|
| 430 | M_BLT_I,
|
|---|
| 431 | M_BLTL_I,
|
|---|
| 432 | M_BLTU,
|
|---|
| 433 | M_BLTUL,
|
|---|
| 434 | M_BLTU_I,
|
|---|
| 435 | M_BLTUL_I,
|
|---|
| 436 | M_BNE,
|
|---|
| 437 | M_BNE_I,
|
|---|
| 438 | M_BNEL_I,
|
|---|
| 439 | M_DABS,
|
|---|
| 440 | M_DADD_I,
|
|---|
| 441 | M_DADDU_I,
|
|---|
| 442 | M_DDIV_3,
|
|---|
| 443 | M_DDIV_3I,
|
|---|
| 444 | M_DDIVU_3,
|
|---|
| 445 | M_DDIVU_3I,
|
|---|
| 446 | M_DIV_3,
|
|---|
| 447 | M_DIV_3I,
|
|---|
| 448 | M_DIVU_3,
|
|---|
| 449 | M_DIVU_3I,
|
|---|
| 450 | M_DLA_AB,
|
|---|
| 451 | M_DLI,
|
|---|
| 452 | M_DMUL,
|
|---|
| 453 | M_DMUL_I,
|
|---|
| 454 | M_DMULO,
|
|---|
| 455 | M_DMULO_I,
|
|---|
| 456 | M_DMULOU,
|
|---|
| 457 | M_DMULOU_I,
|
|---|
| 458 | M_DREM_3,
|
|---|
| 459 | M_DREM_3I,
|
|---|
| 460 | M_DREMU_3,
|
|---|
| 461 | M_DREMU_3I,
|
|---|
| 462 | M_DSUB_I,
|
|---|
| 463 | M_DSUBU_I,
|
|---|
| 464 | M_DSUBU_I_2,
|
|---|
| 465 | M_J_A,
|
|---|
| 466 | M_JAL_1,
|
|---|
| 467 | M_JAL_2,
|
|---|
| 468 | M_JAL_A,
|
|---|
| 469 | M_L_DOB,
|
|---|
| 470 | M_L_DAB,
|
|---|
| 471 | M_LA_AB,
|
|---|
| 472 | M_LB_A,
|
|---|
| 473 | M_LB_AB,
|
|---|
| 474 | M_LBU_A,
|
|---|
| 475 | M_LBU_AB,
|
|---|
| 476 | M_LD_A,
|
|---|
| 477 | M_LD_OB,
|
|---|
| 478 | M_LD_AB,
|
|---|
| 479 | M_LDC1_AB,
|
|---|
| 480 | M_LDC2_AB,
|
|---|
| 481 | M_LDC3_AB,
|
|---|
| 482 | M_LDL_AB,
|
|---|
| 483 | M_LDR_AB,
|
|---|
| 484 | M_LH_A,
|
|---|
| 485 | M_LH_AB,
|
|---|
| 486 | M_LHU_A,
|
|---|
| 487 | M_LHU_AB,
|
|---|
| 488 | M_LI,
|
|---|
| 489 | M_LI_D,
|
|---|
| 490 | M_LI_DD,
|
|---|
| 491 | M_LI_S,
|
|---|
| 492 | M_LI_SS,
|
|---|
| 493 | M_LL_AB,
|
|---|
| 494 | M_LLD_AB,
|
|---|
| 495 | M_LS_A,
|
|---|
| 496 | M_LW_A,
|
|---|
| 497 | M_LW_AB,
|
|---|
| 498 | M_LWC0_A,
|
|---|
| 499 | M_LWC0_AB,
|
|---|
| 500 | M_LWC1_A,
|
|---|
| 501 | M_LWC1_AB,
|
|---|
| 502 | M_LWC2_A,
|
|---|
| 503 | M_LWC2_AB,
|
|---|
| 504 | M_LWC3_A,
|
|---|
| 505 | M_LWC3_AB,
|
|---|
| 506 | M_LWL_A,
|
|---|
| 507 | M_LWL_AB,
|
|---|
| 508 | M_LWR_A,
|
|---|
| 509 | M_LWR_AB,
|
|---|
| 510 | M_LWU_AB,
|
|---|
| 511 | M_MUL,
|
|---|
| 512 | M_MUL_I,
|
|---|
| 513 | M_MULO,
|
|---|
| 514 | M_MULO_I,
|
|---|
| 515 | M_MULOU,
|
|---|
| 516 | M_MULOU_I,
|
|---|
| 517 | M_NOR_I,
|
|---|
| 518 | M_OR_I,
|
|---|
| 519 | M_REM_3,
|
|---|
| 520 | M_REM_3I,
|
|---|
| 521 | M_REMU_3,
|
|---|
| 522 | M_REMU_3I,
|
|---|
| 523 | M_ROL,
|
|---|
| 524 | M_ROL_I,
|
|---|
| 525 | M_ROR,
|
|---|
| 526 | M_ROR_I,
|
|---|
| 527 | M_S_DA,
|
|---|
| 528 | M_S_DOB,
|
|---|
| 529 | M_S_DAB,
|
|---|
| 530 | M_S_S,
|
|---|
| 531 | M_SC_AB,
|
|---|
| 532 | M_SCD_AB,
|
|---|
| 533 | M_SD_A,
|
|---|
| 534 | M_SD_OB,
|
|---|
| 535 | M_SD_AB,
|
|---|
| 536 | M_SDC1_AB,
|
|---|
| 537 | M_SDC2_AB,
|
|---|
| 538 | M_SDC3_AB,
|
|---|
| 539 | M_SDL_AB,
|
|---|
| 540 | M_SDR_AB,
|
|---|
| 541 | M_SEQ,
|
|---|
| 542 | M_SEQ_I,
|
|---|
| 543 | M_SGE,
|
|---|
| 544 | M_SGE_I,
|
|---|
| 545 | M_SGEU,
|
|---|
| 546 | M_SGEU_I,
|
|---|
| 547 | M_SGT,
|
|---|
| 548 | M_SGT_I,
|
|---|
| 549 | M_SGTU,
|
|---|
| 550 | M_SGTU_I,
|
|---|
| 551 | M_SLE,
|
|---|
| 552 | M_SLE_I,
|
|---|
| 553 | M_SLEU,
|
|---|
| 554 | M_SLEU_I,
|
|---|
| 555 | M_SLT_I,
|
|---|
| 556 | M_SLTU_I,
|
|---|
| 557 | M_SNE,
|
|---|
| 558 | M_SNE_I,
|
|---|
| 559 | M_SB_A,
|
|---|
| 560 | M_SB_AB,
|
|---|
| 561 | M_SH_A,
|
|---|
| 562 | M_SH_AB,
|
|---|
| 563 | M_SW_A,
|
|---|
| 564 | M_SW_AB,
|
|---|
| 565 | M_SWC0_A,
|
|---|
| 566 | M_SWC0_AB,
|
|---|
| 567 | M_SWC1_A,
|
|---|
| 568 | M_SWC1_AB,
|
|---|
| 569 | M_SWC2_A,
|
|---|
| 570 | M_SWC2_AB,
|
|---|
| 571 | M_SWC3_A,
|
|---|
| 572 | M_SWC3_AB,
|
|---|
| 573 | M_SWL_A,
|
|---|
| 574 | M_SWL_AB,
|
|---|
| 575 | M_SWR_A,
|
|---|
| 576 | M_SWR_AB,
|
|---|
| 577 | M_SUB_I,
|
|---|
| 578 | M_SUBU_I,
|
|---|
| 579 | M_SUBU_I_2,
|
|---|
| 580 | M_TEQ_I,
|
|---|
| 581 | M_TGE_I,
|
|---|
| 582 | M_TGEU_I,
|
|---|
| 583 | M_TLT_I,
|
|---|
| 584 | M_TLTU_I,
|
|---|
| 585 | M_TNE_I,
|
|---|
| 586 | M_TRUNCWD,
|
|---|
| 587 | M_TRUNCWS,
|
|---|
| 588 | M_ULD,
|
|---|
| 589 | M_ULD_A,
|
|---|
| 590 | M_ULH,
|
|---|
| 591 | M_ULH_A,
|
|---|
| 592 | M_ULHU,
|
|---|
| 593 | M_ULHU_A,
|
|---|
| 594 | M_ULW,
|
|---|
| 595 | M_ULW_A,
|
|---|
| 596 | M_USH,
|
|---|
| 597 | M_USH_A,
|
|---|
| 598 | M_USW,
|
|---|
| 599 | M_USW_A,
|
|---|
| 600 | M_USD,
|
|---|
| 601 | M_USD_A,
|
|---|
| 602 | M_XOR_I,
|
|---|
| 603 | M_COP0,
|
|---|
| 604 | M_COP1,
|
|---|
| 605 | M_COP2,
|
|---|
| 606 | M_COP3,
|
|---|
| 607 | M_NUM_MACROS
|
|---|
| 608 | };
|
|---|
| 609 |
|
|---|
| 610 |
|
|---|
| 611 | /* The order of overloaded instructions matters. Label arguments and
|
|---|
| 612 | register arguments look the same. Instructions that can have either
|
|---|
| 613 | for arguments must apear in the correct order in this table for the
|
|---|
| 614 | assembler to pick the right one. In other words, entries with
|
|---|
| 615 | immediate operands must apear after the same instruction with
|
|---|
| 616 | registers.
|
|---|
| 617 |
|
|---|
| 618 | Many instructions are short hand for other instructions (i.e., The
|
|---|
| 619 | jal <register> instruction is short for jalr <register>). */
|
|---|
| 620 |
|
|---|
| 621 | extern const struct mips_opcode mips_builtin_opcodes[];
|
|---|
| 622 | extern const int bfd_mips_num_builtin_opcodes;
|
|---|
| 623 | extern struct mips_opcode *mips_opcodes;
|
|---|
| 624 | extern int bfd_mips_num_opcodes;
|
|---|
| 625 | #define NUMOPCODES bfd_mips_num_opcodes
|
|---|
| 626 |
|
|---|
| 627 | |
|---|
| 628 |
|
|---|
| 629 | /* The rest of this file adds definitions for the mips16 TinyRISC
|
|---|
| 630 | processor. */
|
|---|
| 631 |
|
|---|
| 632 | /* These are the bitmasks and shift counts used for the different
|
|---|
| 633 | fields in the instruction formats. Other than OP, no masks are
|
|---|
| 634 | provided for the fixed portions of an instruction, since they are
|
|---|
| 635 | not needed.
|
|---|
| 636 |
|
|---|
| 637 | The I format uses IMM11.
|
|---|
| 638 |
|
|---|
| 639 | The RI format uses RX and IMM8.
|
|---|
| 640 |
|
|---|
| 641 | The RR format uses RX, and RY.
|
|---|
| 642 |
|
|---|
| 643 | The RRI format uses RX, RY, and IMM5.
|
|---|
| 644 |
|
|---|
| 645 | The RRR format uses RX, RY, and RZ.
|
|---|
| 646 |
|
|---|
| 647 | The RRI_A format uses RX, RY, and IMM4.
|
|---|
| 648 |
|
|---|
| 649 | The SHIFT format uses RX, RY, and SHAMT.
|
|---|
| 650 |
|
|---|
| 651 | The I8 format uses IMM8.
|
|---|
| 652 |
|
|---|
| 653 | The I8_MOVR32 format uses RY and REGR32.
|
|---|
| 654 |
|
|---|
| 655 | The IR_MOV32R format uses REG32R and MOV32Z.
|
|---|
| 656 |
|
|---|
| 657 | The I64 format uses IMM8.
|
|---|
| 658 |
|
|---|
| 659 | The RI64 format uses RY and IMM5.
|
|---|
| 660 | */
|
|---|
| 661 |
|
|---|
| 662 | #define MIPS16OP_MASK_OP 0x1f
|
|---|
| 663 | #define MIPS16OP_SH_OP 11
|
|---|
| 664 | #define MIPS16OP_MASK_IMM11 0x7ff
|
|---|
| 665 | #define MIPS16OP_SH_IMM11 0
|
|---|
| 666 | #define MIPS16OP_MASK_RX 0x7
|
|---|
| 667 | #define MIPS16OP_SH_RX 8
|
|---|
| 668 | #define MIPS16OP_MASK_IMM8 0xff
|
|---|
| 669 | #define MIPS16OP_SH_IMM8 0
|
|---|
| 670 | #define MIPS16OP_MASK_RY 0x7
|
|---|
| 671 | #define MIPS16OP_SH_RY 5
|
|---|
| 672 | #define MIPS16OP_MASK_IMM5 0x1f
|
|---|
| 673 | #define MIPS16OP_SH_IMM5 0
|
|---|
| 674 | #define MIPS16OP_MASK_RZ 0x7
|
|---|
| 675 | #define MIPS16OP_SH_RZ 2
|
|---|
| 676 | #define MIPS16OP_MASK_IMM4 0xf
|
|---|
| 677 | #define MIPS16OP_SH_IMM4 0
|
|---|
| 678 | #define MIPS16OP_MASK_REGR32 0x1f
|
|---|
| 679 | #define MIPS16OP_SH_REGR32 0
|
|---|
| 680 | #define MIPS16OP_MASK_REG32R 0x1f
|
|---|
| 681 | #define MIPS16OP_SH_REG32R 3
|
|---|
| 682 | #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
|
|---|
| 683 | #define MIPS16OP_MASK_MOVE32Z 0x7
|
|---|
| 684 | #define MIPS16OP_SH_MOVE32Z 0
|
|---|
| 685 | #define MIPS16OP_MASK_IMM6 0x3f
|
|---|
| 686 | #define MIPS16OP_SH_IMM6 5
|
|---|
| 687 |
|
|---|
| 688 | /* These are the characters which may appears in the args field of an
|
|---|
| 689 | instruction. They appear in the order in which the fields appear
|
|---|
| 690 | when the instruction is used. Commas and parentheses in the args
|
|---|
| 691 | string are ignored when assembling, and written into the output
|
|---|
| 692 | when disassembling.
|
|---|
| 693 |
|
|---|
| 694 | "y" 3 bit register (MIPS16OP_*_RY)
|
|---|
| 695 | "x" 3 bit register (MIPS16OP_*_RX)
|
|---|
| 696 | "z" 3 bit register (MIPS16OP_*_RZ)
|
|---|
| 697 | "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
|
|---|
| 698 | "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
|
|---|
| 699 | "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
|
|---|
| 700 | "0" zero register ($0)
|
|---|
| 701 | "S" stack pointer ($sp or $29)
|
|---|
| 702 | "P" program counter
|
|---|
| 703 | "R" return address register ($ra or $31)
|
|---|
| 704 | "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
|
|---|
| 705 | "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
|
|---|
| 706 | "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
|
|---|
| 707 | "a" 26 bit jump address
|
|---|
| 708 | "e" 11 bit extension value
|
|---|
| 709 | "l" register list for entry instruction
|
|---|
| 710 | "L" register list for exit instruction
|
|---|
| 711 |
|
|---|
| 712 | The remaining codes may be extended. Except as otherwise noted,
|
|---|
| 713 | the full extended operand is a 16 bit signed value.
|
|---|
| 714 | "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
|
|---|
| 715 | ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
|
|---|
| 716 | "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
|
|---|
| 717 | "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
|
|---|
| 718 | "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
|
|---|
| 719 | "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
|
|---|
| 720 | "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
|
|---|
| 721 | "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
|
|---|
| 722 | "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
|
|---|
| 723 | "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
|
|---|
| 724 | "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
|
|---|
| 725 | "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
|
|---|
| 726 | "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
|
|---|
| 727 | "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
|
|---|
| 728 | "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
|
|---|
| 729 | "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
|
|---|
| 730 | "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
|
|---|
| 731 | "q" 11 bit branch address (MIPS16OP_*_IMM11)
|
|---|
| 732 | "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
|
|---|
| 733 | "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
|
|---|
| 734 | "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
|
|---|
| 735 | */
|
|---|
| 736 |
|
|---|
| 737 | /* For the mips16, we use the same opcode table format and a few of
|
|---|
| 738 | the same flags. However, most of the flags are different. */
|
|---|
| 739 |
|
|---|
| 740 | /* Modifies the register in MIPS16OP_*_RX. */
|
|---|
| 741 | #define MIPS16_INSN_WRITE_X 0x00000001
|
|---|
| 742 | /* Modifies the register in MIPS16OP_*_RY. */
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| 743 | #define MIPS16_INSN_WRITE_Y 0x00000002
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| 744 | /* Modifies the register in MIPS16OP_*_RZ. */
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|---|
| 745 | #define MIPS16_INSN_WRITE_Z 0x00000004
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| 746 | /* Modifies the T ($24) register. */
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| 747 | #define MIPS16_INSN_WRITE_T 0x00000008
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| 748 | /* Modifies the SP ($29) register. */
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| 749 | #define MIPS16_INSN_WRITE_SP 0x00000010
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|---|
| 750 | /* Modifies the RA ($31) register. */
|
|---|
| 751 | #define MIPS16_INSN_WRITE_31 0x00000020
|
|---|
| 752 | /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
|
|---|
| 753 | #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
|
|---|
| 754 | /* Reads the register in MIPS16OP_*_RX. */
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|---|
| 755 | #define MIPS16_INSN_READ_X 0x00000080
|
|---|
| 756 | /* Reads the register in MIPS16OP_*_RY. */
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|---|
| 757 | #define MIPS16_INSN_READ_Y 0x00000100
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|---|
| 758 | /* Reads the register in MIPS16OP_*_MOVE32Z. */
|
|---|
| 759 | #define MIPS16_INSN_READ_Z 0x00000200
|
|---|
| 760 | /* Reads the T ($24) register. */
|
|---|
| 761 | #define MIPS16_INSN_READ_T 0x00000400
|
|---|
| 762 | /* Reads the SP ($29) register. */
|
|---|
| 763 | #define MIPS16_INSN_READ_SP 0x00000800
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|---|
| 764 | /* Reads the RA ($31) register. */
|
|---|
| 765 | #define MIPS16_INSN_READ_31 0x00001000
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|---|
| 766 | /* Reads the program counter. */
|
|---|
| 767 | #define MIPS16_INSN_READ_PC 0x00002000
|
|---|
| 768 | /* Reads the general purpose register in MIPS16OP_*_REGR32. */
|
|---|
| 769 | #define MIPS16_INSN_READ_GPR_X 0x00004000
|
|---|
| 770 | /* Is a branch insn. */
|
|---|
| 771 | #define MIPS16_INSN_BRANCH 0x00010000
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|---|
| 772 |
|
|---|
| 773 | /* The following flags have the same value for the mips16 opcode
|
|---|
| 774 | table:
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|---|
| 775 | INSN_UNCOND_BRANCH_DELAY
|
|---|
| 776 | INSN_COND_BRANCH_DELAY
|
|---|
| 777 | INSN_COND_BRANCH_LIKELY (never used)
|
|---|
| 778 | INSN_READ_HI
|
|---|
| 779 | INSN_READ_LO
|
|---|
| 780 | INSN_WRITE_HI
|
|---|
| 781 | INSN_WRITE_LO
|
|---|
| 782 | INSN_TRAP
|
|---|
| 783 | INSN_ISA3
|
|---|
| 784 | */
|
|---|
| 785 |
|
|---|
| 786 | extern const struct mips_opcode mips16_opcodes[];
|
|---|
| 787 | extern const int bfd_mips16_num_opcodes;
|
|---|
| 788 |
|
|---|
| 789 | #endif /* _MIPS_H_ */
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