| 1 | /* Table of opcodes for the Motorola M88k family.
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| 2 | Copyright 1989, 1990, 1991, 1993, 2001 Free Software Foundation, Inc.
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| 3 |
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| 4 | This file is part of GDB and GAS.
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| 5 |
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| 6 | This program is free software; you can redistribute it and/or modify
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| 7 | it under the terms of the GNU General Public License as published by
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| 8 | the Free Software Foundation; either version 2 of the License, or
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| 9 | (at your option) any later version.
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| 10 |
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| 11 | This program is distributed in the hope that it will be useful,
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| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 14 | GNU General Public License for more details.
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| 15 |
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| 16 | You should have received a copy of the GNU General Public License
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| 17 | along with this program; if not, write to the Free Software
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| 18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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| 19 |
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| 20 | /*
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| 21 | * Disassembler Instruction Table
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| 22 | *
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| 23 | * The first field of the table is the opcode field. If an opcode
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| 24 | * is specified which has any non-opcode bits on, a system error
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| 25 | * will occur when the system attempts the install it into the
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| 26 | * instruction table. The second parameter is a pointer to the
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| 27 | * instruction mnemonic. Each operand is specified by offset, width,
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| 28 | * and type. The offset is the bit number of the least significant
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| 29 | * bit of the operand with bit 0 being the least significant bit of
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| 30 | * the instruction. The width is the number of bits used to specify
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| 31 | * the operand. The type specifies the output format to be used for
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| 32 | * the operand. The valid formats are: register, register indirect,
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| 33 | * hex constant, and bit field specification. The last field is a
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| 34 | * pointer to the next instruction in the linked list. These pointers
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| 35 | * are initialized by init_disasm().
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| 36 | *
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| 37 | * Revision History
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| 38 | *
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| 39 | * Revision 1.0 11/08/85 Creation date
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| 40 | * 1.1 02/05/86 Updated instruction mnemonic table MD
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| 41 | * 1.2 06/16/86 Updated SIM_FLAGS for floating point
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| 42 | * 1.3 09/20/86 Updated for new encoding
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| 43 | * 05/11/89 R. Trawick adapted from Motorola disassembler
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| 44 | */
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| 45 |
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| 46 | #include <stdio.h>
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| 47 |
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| 48 | /* Define the number of bits in the primary opcode field of the instruction,
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| 49 | the destination field, the source 1 and source 2 fields. */
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| 50 |
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| 51 | /* Size of opcode field. */
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| 52 | #define OP 8
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| 53 |
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| 54 | /* Size of destination. */
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| 55 | #define DEST 6
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| 56 |
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| 57 | /* Size of source1. */
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| 58 | #define SOURCE1 6
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| 59 |
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| 60 | /* Size of source2. */
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| 61 | #define SOURCE2 6
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| 62 |
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| 63 | /* Number of registers. */
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| 64 | #define REGs 32
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| 65 |
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| 66 | /* Type definitions. */
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| 67 |
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| 68 | typedef unsigned int UINT;
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| 69 | #define WORD long
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| 70 | #define FLAG unsigned
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| 71 | #define STATE short
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| 72 |
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| 73 | /* The next four equates define the priorities that the various classes
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| 74 | * of instructions have regarding writing results back into registers and
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| 75 | * signalling exceptions. */
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| 76 |
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| 77 | /* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */
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| 78 | #undef PMEM
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| 79 |
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| 80 | /* Integer priority. */
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| 81 | #define PINT 0
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| 82 |
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| 83 | /* Floating point priority. */
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| 84 | #define PFLT 1
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| 85 |
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| 86 | /* Memory priority. */
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| 87 | #define PMEM 2
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| 88 |
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| 89 | /* Not applicable, instruction doesn't write to regs. */
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| 90 | #define NA 3
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| 91 |
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| 92 | /* Highest of these priorities. */
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| 93 | #define HIPRI 3
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| 94 |
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| 95 | /* The instruction registers are an artificial mechanism to speed up
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| 96 | * simulator execution. In the real processor, an instruction register
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| 97 | * is 32 bits wide. In the simulator, the 32 bit instruction is kept in
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| 98 | * a structure field called rawop, and the instruction is partially decoded,
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| 99 | * and split into various fields and flags which make up the other fields
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| 100 | * of the structure.
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| 101 | * The partial decode is done when the instructions are initially loaded
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| 102 | * into simulator memory. The simulator code memory is not an array of
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| 103 | * 32 bit words, but is an array of instruction register structures.
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| 104 | * Yes this wastes memory, but it executes much quicker.
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| 105 | */
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| 106 |
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| 107 | struct IR_FIELDS
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| 108 | {
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| 109 | unsigned op:OP,
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| 110 | dest: DEST,
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| 111 | src1: SOURCE1,
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| 112 | src2: SOURCE2;
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| 113 | int ltncy,
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| 114 | extime,
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| 115 | /* Writeback priority. */
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| 116 | wb_pri;
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| 117 | /* Immediate size. */
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| 118 | unsigned imm_flags:2,
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| 119 | /* Register source 1 used. */
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| 120 | rs1_used:1,
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| 121 | /* Register source 2 used. */
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