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1This is as.info, produced by makeinfo version 4.0 from as.texinfo.
2
3START-INFO-DIR-ENTRY
4* As: (as). The GNU assembler.
5END-INFO-DIR-ENTRY
6
7 This file documents the GNU Assembler "as".
8
9 Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001 Free
10Software Foundation, Inc.
11
12 Permission is granted to copy, distribute and/or modify this document
13 under the terms of the GNU Free Documentation License, Version 1.1
14 or any later version published by the Free Software Foundation;
15 with no Invariant Sections, with no Front-Cover Texts, and with no
16 Back-Cover Texts. A copy of the license is included in the
17section entitled "GNU Free Documentation License".
18
19
20File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent
21
22Opcodes
23-------
24
25 For detailed information on the SH machine instruction set, see
26`SH-Microcomputer User's Manual' (Hitachi Micro Systems, Inc.).
27
28 `as' implements all the standard SH opcodes. No additional
29pseudo-instructions are needed on this family. Note, however, that
30because `as' supports a simpler form of PC-relative addressing, you may
31simply write (for example)
32
33 mov.l bar,r0
34
35where other assemblers might require an explicit displacement to `bar'
36from the program counter:
37
38 mov.l @(DISP, PC)
39
40 Here is a summary of SH opcodes:
41
42 Legend:
43 Rn a numbered register
44 Rm another numbered register
45 #imm immediate data
46 disp displacement
47 disp8 8-bit displacement
48 disp12 12-bit displacement
49
50 add #imm,Rn lds.l @Rn+,PR
51 add Rm,Rn mac.w @Rm+,@Rn+
52 addc Rm,Rn mov #imm,Rn
53 addv Rm,Rn mov Rm,Rn
54 and #imm,R0 mov.b Rm,@(R0,Rn)
55 and Rm,Rn mov.b Rm,@-Rn
56 and.b #imm,@(R0,GBR) mov.b Rm,@Rn
57 bf disp8 mov.b @(disp,Rm),R0
58 bra disp12 mov.b @(disp,GBR),R0
59 bsr disp12 mov.b @(R0,Rm),Rn
60 bt disp8 mov.b @Rm+,Rn
61 clrmac mov.b @Rm,Rn
62 clrt mov.b R0,@(disp,Rm)
63 cmp/eq #imm,R0 mov.b R0,@(disp,GBR)
64 cmp/eq Rm,Rn mov.l Rm,@(disp,Rn)
65 cmp/ge Rm,Rn mov.l Rm,@(R0,Rn)
66 cmp/gt Rm,Rn mov.l Rm,@-Rn
67 cmp/hi Rm,Rn mov.l Rm,@Rn
68 cmp/hs Rm,Rn mov.l @(disp,Rn),Rm
69 cmp/pl Rn mov.l @(disp,GBR),R0
70 cmp/pz Rn mov.l @(disp,PC),Rn
71 cmp/str Rm,Rn mov.l @(R0,Rm),Rn
72 div0s Rm,Rn mov.l @Rm+,Rn
73 div0u mov.l @Rm,Rn
74 div1 Rm,Rn mov.l R0,@(disp,GBR)
75 exts.b Rm,Rn mov.w Rm,@(R0,Rn)
76 exts.w Rm,Rn mov.w Rm,@-Rn
77 extu.b Rm,Rn mov.w Rm,@Rn
78 extu.w Rm,Rn mov.w @(disp,Rm),R0
79 jmp @Rn mov.w @(disp,GBR),R0
80 jsr @Rn mov.w @(disp,PC),Rn
81 ldc Rn,GBR mov.w @(R0,Rm),Rn
82 ldc Rn,SR mov.w @Rm+,Rn
83 ldc Rn,VBR mov.w @Rm,Rn
84 ldc.l @Rn+,GBR mov.w R0,@(disp,Rm)
85 ldc.l @Rn+,SR mov.w R0,@(disp,GBR)
86 ldc.l @Rn+,VBR mova @(disp,PC),R0
87 lds Rn,MACH movt Rn
88 lds Rn,MACL muls Rm,Rn
89 lds Rn,PR mulu Rm,Rn
90 lds.l @Rn+,MACH neg Rm,Rn
91 lds.l @Rn+,MACL negc Rm,Rn
92
93 nop stc VBR,Rn
94 not Rm,Rn stc.l GBR,@-Rn
95 or #imm,R0 stc.l SR,@-Rn
96 or Rm,Rn stc.l VBR,@-Rn
97 or.b #imm,@(R0,GBR) sts MACH,Rn
98 rotcl Rn sts MACL,Rn
99 rotcr Rn sts PR,Rn
100 rotl Rn sts.l MACH,@-Rn
101 rotr Rn sts.l MACL,@-Rn
102 rte sts.l PR,@-Rn
103 rts sub Rm,Rn
104 sett subc Rm,Rn
105 shal Rn subv Rm,Rn
106 shar Rn swap.b Rm,Rn
107 shll Rn swap.w Rm,Rn
108 shll16 Rn tas.b @Rn
109 shll2 Rn trapa #imm
110 shll8 Rn tst #imm,R0
111 shlr Rn tst Rm,Rn
112 shlr16 Rn tst.b #imm,@(R0,GBR)
113 shlr2 Rn xor #imm,R0
114 shlr8 Rn xor Rm,Rn
115 sleep xor.b #imm,@(R0,GBR)
116 stc GBR,Rn xtrct Rm,Rn
117 stc SR,Rn
118
119
120File: as.info, Node: Sparc-Dependent, Next: V850-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies
121
122SPARC Dependent Features
123========================
124
125* Menu:
126
127* Sparc-Opts:: Options
128* Sparc-Aligned-Data:: Option to enforce aligned data
129* Sparc-Float:: Floating Point
130* Sparc-Directives:: Sparc Machine Directives
131
132
133File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent
134
135Options
136-------
137
138 The SPARC chip family includes several successive levels, using the
139same core instruction set, but including a few additional instructions
140at each level. There are exceptions to this however. For details on
141what instructions each variant supports, please see the chip's
142architecture reference manual.
143
144 By default, `as' assumes the core instruction set (SPARC v6), but
145"bumps" the architecture level as needed: it switches to successively
146higher architectures as it encounters instructions that only exist in
147the higher levels.
148
149 If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump
150passed sparclite by default, an option must be passed to enable the v9
151instructions.
152
153 GAS treats sparclite as being compatible with v8, unless an
154architecture is explicitly requested. SPARC v9 is always incompatible
155with sparclite.
156
157`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
158`-Av8plus | -Av8plusa | -Av9 | -Av9a'
159 Use one of the `-A' options to select one of the SPARC
160 architectures explicitly. If you select an architecture
161 explicitly, `as' reports a fatal error if it encounters an
162 instruction or feature requiring an incompatible or higher level.
163
164 `-Av8plus' and `-Av8plusa' select a 32 bit environment.
165
166 `-Av9' and `-Av9a' select a 64 bit environment and are not
167 available unless GAS is explicitly configured with 64 bit
168 environment support.
169
170 `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
171 UltraSPARC extensions.
172
173`-xarch=v8plus | -xarch=v8plusa'
174 For compatibility with the Solaris v9 assembler. These options are
175 equivalent to -Av8plus and -Av8plusa, respectively.
176
177`-bump'
178 Warn whenever it is necessary to switch to another level. If an
179 architecture level is explicitly requested, GAS will not issue
180 warnings until that level is reached, and will then bump the level
181 as required (except between incompatible levels).
182
183`-32 | -64'
184 Select the word size, either 32 bits or 64 bits. These options
185 are only available with the ELF object file format, and require
186 that the necessary BFD support has been included.
187
188
189File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Float, Prev: Sparc-Opts, Up: Sparc-Dependent
190
191Enforcing aligned data
192----------------------
193
194 SPARC GAS normally permits data to be misaligned. For example, it
195permits the `.long' pseudo-op to be used on a byte boundary. However,
196the native SunOS and Solaris assemblers issue an error when they see
197misaligned data.
198
199 You can use the `--enforce-aligned-data' option to make SPARC GAS
200also issue an error about misaligned data, just as the SunOS and Solaris
201assemblers do.
202
203 The `--enforce-aligned-data' option is not the default because gcc
204issues misaligned data pseudo-ops when it initializes certain packed
205data structures (structures defined using the `packed' attribute). You
206may have to assemble with GAS in order to initialize packed data
207structures in your own code.
208
209
210File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent
211
212Floating Point
213--------------
214
215 The Sparc uses IEEE floating-point numbers.
216
217
218File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent
219
220Sparc Machine Directives
221------------------------
222
223 The Sparc version of `as' supports the following additional machine
224directives:
225
226`.align'
227 This must be followed by the desired alignment in bytes.
228
229`.common'
230 This must be followed by a symbol name, a positive number, and
231 `"bss"'. This behaves somewhat like `.comm', but the syntax is
232 different.
233
234`.half'
235 This is functionally identical to `.short'.
236
237`.nword'
238 On the Sparc, the `.nword' directive produces native word sized
239 value, ie. if assembling with -32 it is equivalent to `.word', if
240 assembling with -64 it is equivalent to `.xword'.
241
242`.proc'
243 This directive is ignored. Any text following it on the same line
244 is also ignored.
245
246`.register'
247 This directive declares use of a global application or system
248 register. It must be followed by a register name %g2, %g3, %g6 or
249 %g7, comma and the symbol name for that register. If symbol name
250 is `#scratch', it is a scratch register, if it is `#ignore', it
251 just surpresses any errors about using undeclared global register,
252 but does not emit any information about it into the object file.
253 This can be useful e.g. if you save the register before use and
254 restore it after.
255
256`.reserve'
257 This must be followed by a symbol name, a positive number, and
258 `"bss"'. This behaves somewhat like `.lcomm', but the syntax is
259 different.
260
261`.seg'
262 This must be followed by `"text"', `"data"', or `"data1"'. It
263 behaves like `.text', `.data', or `.data 1'.
264
265`.skip'
266 This is functionally identical to the `.space' directive.
267
268`.word'
269 On the Sparc, the `.word' directive produces 32 bit values,
270 instead of the 16 bit values it produces on many other machines.
271
272`.xword'
273 On the Sparc V9 processor, the `.xword' directive produces 64 bit
274 values.
275
276
277File: as.info, Node: Z8000-Dependent, Next: Vax-Dependent, Prev: V850-Dependent, Up: Machine Dependencies
278
279Z8000 Dependent Features
280========================
281
282 The Z8000 as supports both members of the Z8000 family: the
283unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with
28424 bit addresses.
285
286 When the assembler is in unsegmented mode (specified with the
287`unsegm' directive), an address takes up one word (16 bit) sized
288register. When the assembler is in segmented mode (specified with the
289`segm' directive), a 24-bit address takes up a long (32 bit) register.
290*Note Assembler Directives for the Z8000: Z8000 Directives, for a list
291of other Z8000 specific assembler directives.
292
293* Menu:
294
295* Z8000 Options:: No special command-line options for Z8000
296* Z8000 Syntax:: Assembler syntax for the Z8000
297* Z8000 Directives:: Special directives for the Z8000
298* Z8000 Opcodes:: Opcodes
299
300
301File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent
302
303Options
304-------
305
306 `as' has no additional command-line options for the Zilog Z8000
307family.
308
309
310File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent
311
312Syntax
313------
314
315* Menu:
316
317* Z8000-Chars:: Special Characters
318* Z8000-Regs:: Register Names
319* Z8000-Addressing:: Addressing Modes
320
321
322File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax
323
324Special Characters
325..................
326
327 `!' is the line comment character.
328
329 You can use `;' instead of a newline to separate statements.
330
331
332File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax
333
334Register Names
335..............
336
337 The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can
338refer to different sized groups of registers by register number, with
339the prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq'
340for 64 bit registers. You can also refer to the contents of the first
341eight (of the sixteen 16 bit registers) by bytes. They are named `rNh'
342and `rNl'.
343
344_byte registers_
345 r0l r0h r1h r1l r2h r2l r3h r3l
346 r4h r4l r5h r5l r6h r6l r7h r7l
347
348_word registers_
349 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
350
351_long word registers_
352 rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
353
354_quad word registers_
355 rq0 rq4 rq8 rq12
356
357
358File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax
359
360Addressing Modes
361................
362
363 as understands the following addressing modes for the Z8000:
364
365`rN'
366 Register direct
367
368`@rN'
369 Indirect register
370
371`ADDR'
372 Direct: the 16 bit or 24 bit address (depending on whether the
373 assembler is in segmented or unsegmented mode) of the operand is
374 in the instruction.
375
376`address(rN)'
377 Indexed: the 16 or 24 bit address is added to the 16 bit register
378 to produce the final address in memory of the operand.
379
380`rN(#IMM)'
381 Base Address: the 16 or 24 bit register is added to the 16 bit sign
382 extended immediate displacement to produce the final address in
383 memory of the operand.
384
385`rN(rM)'
386 Base Index: the 16 or 24 bit register rN is added to the sign
387 extended 16 bit index register rM to produce the final address in
388 memory of the operand.
389
390`#XX'
391 Immediate data XX.
392
393
394File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent
395
396Assembler Directives for the Z8000
397----------------------------------
398
399 The Z8000 port of as includes these additional assembler directives,
400for compatibility with other Z8000 assemblers. As shown, these do not
401begin with `.' (unlike the ordinary as directives).
402
403`segm'
404 Generates code for the segmented Z8001.
405
406`unsegm'
407 Generates code for the unsegmented Z8002.
408
409`name'
410 Synonym for `.file'
411
412`global'
413 Synonym for `.global'
414
415`wval'
416 Synonym for `.word'
417
418`lval'
419 Synonym for `.long'
420
421`bval'
422 Synonym for `.byte'
423
424`sval'
425 Assemble a string. `sval' expects one string literal, delimited by
426 single quotes. It assembles each byte of the string into
427 consecutive addresses. You can use the escape sequence `%XX'
428 (where XX represents a two-digit hexadecimal number) to represent
429 the character whose ASCII value is XX. Use this feature to
430 describe single quote and other characters that may not appear in
431 string literals as themselves. For example, the C statement
432 `char *a = "he said \"it's 50% off\"";' is represented in Z8000
433 assembly language (shown with the assembler output in hex at the
434 left) as
435
436 68652073 sval 'he said %22it%27s 50%25 off%22%00'
437 61696420
438 22697427
439 73203530
440 25206F66
441 662200
442
443`rsect'
444 synonym for `.section'
445
446`block'
447 synonym for `.space'
448
449`even'
450 special case of `.align'; aligns output to even byte boundary.
451
452
453File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent
454
455Opcodes
456-------
457
458 For detailed information on the Z8000 machine instruction set, see
459`Z8000 Technical Manual'.
460
461 The following table summarizes the opcodes and their arguments:
462
463 rs 16 bit source register
464 rd 16 bit destination register
465 rbs 8 bit source register
466 rbd 8 bit destination register
467 rrs 32 bit source register
468 rrd 32 bit destination register
469 rqs 64 bit source register
470 rqd 64 bit destination register
471 addr 16/24 bit address
472 imm immediate data
473
474 adc rd,rs clrb addr cpsir @rd,@rs,rr,cc
475 adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc
476 add rd,@rs clrb rbd dab rbd
477 add rd,addr com @rd dbjnz rbd,disp7
478 add rd,addr(rs) com addr dec @rd,imm4m1
479 add rd,imm16 com addr(rd) dec addr(rd),imm4m1
480 add rd,rs com rd dec addr,imm4m1
481 addb rbd,@rs comb @rd dec rd,imm4m1
482 addb rbd,addr comb addr decb @rd,imm4m1
483 addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1
484 addb rbd,imm8 comb rbd decb addr,imm4m1
485 addb rbd,rbs comflg flags decb rbd,imm4m1
486 addl rrd,@rs cp @rd,imm16 di i2
487 addl rrd,addr cp addr(rd),imm16 div rrd,@rs
488 addl rrd,addr(rs) cp addr,imm16 div rrd,addr
489 addl rrd,imm32 cp rd,@rs div rrd,addr(rs)
490 addl rrd,rrs cp rd,addr div rrd,imm16
491 and rd,@rs cp rd,addr(rs) div rrd,rs
492 and rd,addr cp rd,imm16 divl rqd,@rs
493 and rd,addr(rs) cp rd,rs divl rqd,addr
494 and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs)
495 and rd,rs cpb addr(rd),imm8 divl rqd,imm32
496 andb rbd,@rs cpb addr,imm8 divl rqd,rrs
497 andb rbd,addr cpb rbd,@rs djnz rd,disp7
498 andb rbd,addr(rs) cpb rbd,addr ei i2
499 andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs
500 andb rbd,rbs cpb rbd,imm8 ex rd,addr
501 bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs)
502 bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs
503 bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs
504 bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr
505 bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs)
506 bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs
507 bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8
508 bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8
509 bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8
510 bitb rbd,rs cpl rrd,@rs ext8f imm8
511 bpt cpl rrd,addr exts rrd
512 call @rd cpl rrd,addr(rs) extsb rd
513 call addr cpl rrd,imm32 extsl rqd
514 call addr(rd) cpl rrd,rrs halt
515 calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs
516 clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16
517 clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs
518 clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16
519 clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1
520 clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1
521 inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs)
522 inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16
523 incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs
524 incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs
525 incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr
526 incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs)
527 ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32
528 indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs
529 inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd
530 inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr
531 iret ldib @rd,@rs,rr neg addr(rd)
532 jp cc,@rd ldir @rd,@rs,rr neg rd
533 jp cc,addr ldirb @rd,@rs,rr negb @rd
534 jp cc,addr(rd) ldk rd,imm4 negb addr
535 jr cc,disp8 ldl @rd,rrs negb addr(rd)
536 ld @rd,imm16 ldl addr(rd),rrs negb rbd
537 ld @rd,rs ldl addr,rrs nop
538 ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs
539 ld addr(rd),rs ldl rd(rx),rrs or rd,addr
540 ld addr,imm16 ldl rrd,@rs or rd,addr(rs)
541 ld addr,rs ldl rrd,addr or rd,imm16
542 ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs
543 ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs
544 ld rd,@rs ldl rrd,rrs orb rbd,addr
545 ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs)
546 ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8
547 ld rd,imm16 ldm @rd,rs,n orb rbd,rbs
548 ld rd,rs ldm addr(rd),rs,n out @rd,rs
549 ld rd,rs(imm16) ldm addr,rs,n out imm16,rs
550 ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs
551 lda rd,addr ldm rd,addr(rs),n outb imm16,rbs
552 lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra
553 lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba
554 lda rd,rs(rx) ldps addr outib @rd,@rs,ra
555 ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra
556 ldb @rd,imm8 ldr disp16,rs pop @rd,@rs
557 ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs
558 ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs
559 ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs
560 ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs
561 ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs
562 ldb rbd,@rs mbit popl addr,@rs
563 ldb rbd,addr mreq rd popl rrd,@rs
564 ldb rbd,addr(rs) mres push @rd,@rs
565 ldb rbd,imm8 mset push @rd,addr
566 ldb rbd,rbs mult rrd,@rs push @rd,addr(rs)
567 ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16
568 push @rd,rs set addr,imm4 subl rrd,imm32
569 pushl @rd,@rs set rd,imm4 subl rrd,rrs
570 pushl @rd,addr set rd,rs tcc cc,rd
571 pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd
572 pushl @rd,rrs setb addr(rd),imm4 test @rd
573 res @rd,imm4 setb addr,imm4 test addr
574 res addr(rd),imm4 setb rbd,imm4 test addr(rd)
575 res addr,imm4 setb rbd,rs test rd
576 res rd,imm4 setflg imm4 testb @rd
577 res rd,rs sinb rbd,imm16 testb addr
578 resb @rd,imm4 sinb rd,imm16 testb addr(rd)
579 resb addr(rd),imm4 sind @rd,@rs,ra testb rbd
580 resb addr,imm4 sindb @rd,@rs,rba testl @rd
581 resb rbd,imm4 sinib @rd,@rs,ra testl addr
582 resb rbd,rs sinibr @rd,@rs,ra testl addr(rd)
583 resflg imm4 sla rd,imm8 testl rrd
584 ret cc slab rbd,imm8 trdb @rd,@rs,rba
585 rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba
586 rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr
587 rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr
588 rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr
589 rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr
590 rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr
591 rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr
592 rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd
593 rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr
594 rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd)
595 rsvd36 sra rd,imm8 tset rd
596 rsvd38 srab rbd,imm8 tsetb @rd
597 rsvd78 sral rrd,imm8 tsetb addr
598 rsvd7e srl rd,imm8 tsetb addr(rd)
599 rsvd9d srlb rbd,imm8 tsetb rbd
600 rsvd9f srll rrd,imm8 xor rd,@rs
601 rsvdb9 sub rd,@rs xor rd,addr
602 rsvdbf sub rd,addr xor rd,addr(rs)
603 sbc rd,rs sub rd,addr(rs) xor rd,imm16
604 sbcb rbd,rbs sub rd,imm16 xor rd,rs
605 sc imm8 sub rd,rs xorb rbd,@rs
606 sda rd,rs subb rbd,@rs xorb rbd,addr
607 sdab rbd,rs subb rbd,addr xorb rbd,addr(rs)
608 sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8
609 sdl rd,rs subb rbd,imm8 xorb rbd,rbs
610 sdlb rbd,rs subb rbd,rbs xorb rbd,rbs
611 sdll rrd,rs subl rrd,@rs
612 set @rd,imm4 subl rrd,addr
613 set addr(rd),imm4 subl rrd,addr(rs)
614
615
616File: as.info, Node: Vax-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies
617
618VAX Dependent Features
619======================
620
621* Menu:
622
623* VAX-Opts:: VAX Command-Line Options
624* VAX-float:: VAX Floating Point
625* VAX-directives:: Vax Machine Directives
626* VAX-opcodes:: VAX Opcodes
627* VAX-branch:: VAX Branch Improvement
628* VAX-operands:: VAX Operands
629* VAX-no:: Not Supported on VAX
630
631
632File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent
633
634VAX Command-Line Options
635------------------------
636
637 The Vax version of `as' accepts any of the following options, gives
638a warning message that the option was ignored and proceeds. These
639options are for compatibility with scripts designed for other people's
640assemblers.
641
642``-D' (Debug)'
643``-S' (Symbol Table)'
644``-T' (Token Trace)'
645 These are obsolete options used to debug old assemblers.
646
647``-d' (Displacement size for JUMPs)'
648 This option expects a number following the `-d'. Like options
649 that expect filenames, the number may immediately follow the `-d'
650 (old standard) or constitute the whole of the command line
651 argument that follows `-d' (GNU standard).
652
653``-V' (Virtualize Interpass Temporary File)'
654 Some other assemblers use a temporary file. This option commanded
655 them to keep the information in active memory rather than in a
656 disk file. `as' always does this, so this option is redundant.
657
658``-J' (JUMPify Longer Branches)'
659 Many 32-bit computers permit a variety of branch instructions to
660 do the same job. Some of these instructions are short (and fast)
661 but have a limited range; others are long (and slow) but can
662 branch anywhere in virtual memory. Often there are 3 flavors of
663 branch: short, medium and long. Some other assemblers would emit
664 short and medium branches, unless told by this option to emit
665 short and long branches.
666
667``-t' (Temporary File Directory)'
668 Some other assemblers may use a temporary file, and this option
669 takes a filename being the directory to site the temporary file.
670 Since `as' does not use a temporary disk file, this option makes
671 no difference. `-t' needs exactly one filename.
672
673 The Vax version of the assembler accepts additional options when
674compiled for VMS:
675
676`-h N'
677 External symbol or section (used for global variables) names are
678 not case sensitive on VAX/VMS and always mapped to upper case.
679 This is contrary to the C language definition which explicitly
680 distinguishes upper and lower case. To implement a standard
681 conforming C compiler, names must be changed (mapped) to preserve
682 the case information. The default mapping is to convert all lower
683 case characters to uppercase and adding an underscore followed by
684 a 6 digit hex value, representing a 24 digit binary value. The
685 one digits in the binary value represent which characters are
686 uppercase in the original symbol name.
687
688 The `-h N' option determines how we map names. This takes several
689 values. No `-h' switch at all allows case hacking as described
690 above. A value of zero (`-h0') implies names should be upper
691 case, and inhibits the case hack. A value of 2 (`-h2') implies
692 names should be all lower case, with no case hack. A value of 3
693 (`-h3') implies that case should be preserved. The value 1 is
694 unused. The `-H' option directs `as' to display every mapped
695 symbol during assembly.
696
697 Symbols whose names include a dollar sign `$' are exceptions to the
698 general name mapping. These symbols are normally only used to
699 reference VMS library names. Such symbols are always mapped to
700 upper case.
701
702`-+'
703 The `-+' option causes `as' to truncate any symbol name larger
704 than 31 characters. The `-+' option also prevents some code
705 following the `_main' symbol normally added to make the object
706 file compatible with Vax-11 "C".
707
708`-1'
709 This option is ignored for backward compatibility with `as'
710 version 1.x.
711
712`-H'
713 The `-H' option causes `as' to print every symbol which was
714 changed by case mapping.
715
716
717File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent
718
719VAX Floating Point
720------------------
721
722 Conversion of flonums to floating point is correct, and compatible
723with previous assemblers. Rounding is towards zero if the remainder is
724exactly half the least significant bit.
725
726 `D', `F', `G' and `H' floating point formats are understood.
727
728 Immediate floating literals (_e.g._ `S`$6.9') are rendered
729correctly. Again, rounding is towards zero in the boundary case.
730
731 The `.float' directive produces `f' format numbers. The `.double'
732directive produces `d' format numbers.
733
734
735File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent
736
737Vax Machine Directives
738----------------------
739
740 The Vax version of the assembler supports four directives for
741generating Vax floating point constants. They are described in the
742table below.
743
744`.dfloat'
745 This expects zero or more flonums, separated by commas, and
746 assembles Vax `d' format 64-bit floating point constants.
747
748`.ffloat'
749 This expects zero or more flonums, separated by commas, and
750 assembles Vax `f' format 32-bit floating point constants.
751
752`.gfloat'
753 This expects zero or more flonums, separated by commas, and
754 assembles Vax `g' format 64-bit floating point constants.
755
756`.hfloat'
757 This expects zero or more flonums, separated by commas, and
758 assembles Vax `h' format 128-bit floating point constants.
759
760
761File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent
762
763VAX Opcodes
764-----------
765
766 All DEC mnemonics are supported. Beware that `case...' instructions
767have exactly 3 operands. The dispatch table that follows the `case...'
768instruction should be made with `.word' statements. This is compatible
769with all unix assemblers we know of.
770
771
772File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent
773
774VAX Branch Improvement
775----------------------
776
777 Certain pseudo opcodes are permitted. They are for branch
778instructions. They expand to the shortest branch instruction that
779reaches the target. Generally these mnemonics are made by substituting
780`j' for `b' at the start of a DEC mnemonic. This feature is included
781both for compatibility and to help compilers. If you do not need this
782feature, avoid these opcodes. Here are the mnemonics, and the code
783they can expand into.
784
785`jbsb'
786 `Jsb' is already an instruction mnemonic, so we chose `jbsb'.
787 (byte displacement)
788 `bsbb ...'
789
790 (word displacement)
791 `bsbw ...'
792
793 (long displacement)
794 `jsb ...'
795
796`jbr'
797`jr'
798 Unconditional branch.
799 (byte displacement)
800 `brb ...'
801
802 (word displacement)
803 `brw ...'
804
805 (long displacement)
806 `jmp ...'
807
808`jCOND'
809 COND may be any one of the conditional branches `neq', `nequ',
810 `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs',
811 `gequ', `cc', `lssu', `cs'. COND may also be one of the bit tests
812 `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs',
813 `lbc'. NOTCOND is the opposite condition to COND.
814 (byte displacement)
815 `bCOND ...'
816
817 (word displacement)
818 `bNOTCOND foo ; brw ... ; foo:'
819
820 (long displacement)
821 `bNOTCOND foo ; jmp ... ; foo:'
822
823`jacbX'
824 X may be one of `b d f g h l w'.
825 (word displacement)
826 `OPCODE ...'
827
828 (long displacement)
829 OPCODE ..., foo ;
830 brb bar ;
831 foo: jmp ... ;
832 bar:
833
834`jaobYYY'
835 YYY may be one of `lss leq'.
836
837`jsobZZZ'
838 ZZZ may be one of `geq gtr'.
839 (byte displacement)
840 `OPCODE ...'
841
842 (word displacement)
843 OPCODE ..., foo ;
844 brb bar ;
845 foo: brw DESTINATION ;
846 bar:
847
848 (long displacement)
849 OPCODE ..., foo ;
850 brb bar ;
851 foo: jmp DESTINATION ;
852 bar:
853
854`aobleq'
855`aoblss'
856`sobgeq'
857`sobgtr'
858
859 (byte displacement)
860 `OPCODE ...'
861
862 (word displacement)
863 OPCODE ..., foo ;
864 brb bar ;
865 foo: brw DESTINATION ;
866 bar:
867
868 (long displacement)
869 OPCODE ..., foo ;
870 brb bar ;
871 foo: jmp DESTINATION ;
872 bar:
873
874
875File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent
876
877VAX Operands
878------------
879
880 The immediate character is `$' for Unix compatibility, not `#' as
881DEC writes it.
882
883 The indirect character is `*' for Unix compatibility, not `@' as DEC
884writes it.
885
886 The displacement sizing character is ``' (an accent grave) for Unix
887compatibility, not `^' as DEC writes it. The letter preceding ``' may
888have either case. `G' is not understood, but all other letters (`b i l
889s w') are understood.
890
891 Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'. Upper
892and lower case letters are equivalent.
893
894 For instance
895 tstb *w`$4(r5)
896
897 Any expression is permitted in an operand. Operands are comma
898separated.
899
900
901File: as.info, Node: VAX-no, Prev: VAX-operands, Up: Vax-Dependent
902
903Not Supported on VAX
904--------------------
905
906 Vax bit fields can not be assembled with `as'. Someone can add the
907required code if they really need it.
908
909
910File: as.info, Node: V850-Dependent, Next: Z8000-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies
911
912v850 Dependent Features
913=======================
914
915* Menu:
916
917* V850 Options:: Options
918* V850 Syntax:: Syntax
919* V850 Floating Point:: Floating Point
920* V850 Directives:: V850 Machine Directives
921* V850 Opcodes:: Opcodes
922
923
924File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent
925
926Options
927-------
928
929 `as' supports the following additional command-line options for the
930V850 processor family:
931
932`-wsigned_overflow'
933 Causes warnings to be produced when signed immediate values
934 overflow the space available for then within their opcodes. By
935 default this option is disabled as it is possible to receive
936 spurious warnings due to using exact bit patterns as immediate
937 constants.
938
939`-wunsigned_overflow'
940 Causes warnings to be produced when unsigned immediate values
941 overflow the space available for then within their opcodes. By
942 default this option is disabled as it is possible to receive
943 spurious warnings due to using exact bit patterns as immediate
944 constants.
945
946`-mv850'
947 Specifies that the assembled code should be marked as being
948 targeted at the V850 processor. This allows the linker to detect
949 attempts to link such code with code assembled for other
950 processors.
951
952`-mv850e'
953 Specifies that the assembled code should be marked as being
954 targeted at the V850E processor. This allows the linker to detect
955 attempts to link such code with code assembled for other
956 processors.
957
958`-mv850any'
959 Specifies that the assembled code should be marked as being
960 targeted at the V850 processor but support instructions that are
961 specific to the extended variants of the process. This allows the
962 production of binaries that contain target specific code, but
963 which are also intended to be used in a generic fashion. For
964 example libgcc.a contains generic routines used by the code
965 produced by GCC for all versions of the v850 architecture,
966 together with support routines only used by the V850E architecture.
967
968
969File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent
970
971Syntax
972------
973
974* Menu:
975
976* V850-Chars:: Special Characters
977* V850-Regs:: Register Names
978
979
980File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax
981
982Special Characters
983..................
984
985 `#' is the line comment character.
986
987
988File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax
989
990Register Names
991..............
992
993 `as' supports the following names for registers:
994`general register 0'
995 r0, zero
996
997`general register 1'
998 r1
999
1000`general register 2'
1001 r2, hp
1002
1003`general register 3'
1004 r3, sp
1005
1006`general register 4'
1007 r4, gp
1008
1009`general register 5'
1010 r5, tp
1011
1012`general register 6'
1013 r6
1014
1015`general register 7'
1016 r7
1017
1018`general register 8'
1019 r8
1020
1021`general register 9'
1022 r9
1023
1024`general register 10'
1025 r10
1026
1027`general register 11'
1028 r11
1029
1030`general register 12'
1031 r12
1032
1033`general register 13'
1034 r13
1035
1036`general register 14'
1037 r14
1038
1039`general register 15'
1040 r15
1041
1042`general register 16'
1043 r16
1044
1045`general register 17'
1046 r17
1047
1048`general register 18'
1049 r18
1050
1051`general register 19'
1052 r19
1053
1054`general register 20'
1055 r20
1056
1057`general register 21'
1058 r21
1059
1060`general register 22'
1061 r22
1062
1063`general register 23'
1064 r23
1065
1066`general register 24'
1067 r24
1068
1069`general register 25'
1070 r25
1071
1072`general register 26'
1073 r26
1074
1075`general register 27'
1076 r27
1077
1078`general register 28'
1079 r28
1080
1081`general register 29'
1082 r29
1083
1084`general register 30'
1085 r30, ep
1086
1087`general register 31'
1088 r31, lp
1089
1090`system register 0'
1091 eipc
1092
1093`system register 1'
1094 eipsw
1095
1096`system register 2'
1097 fepc
1098
1099`system register 3'
1100 fepsw
1101
1102`system register 4'
1103 ecr
1104
1105`system register 5'
1106 psw
1107
1108`system register 16'
1109 ctpc
1110
1111`system register 17'
1112 ctpsw
1113
1114`system register 18'
1115 dbpc
1116
1117`system register 19'
1118 dbpsw
1119
1120`system register 20'
1121 ctbp
1122
1123
1124File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent
1125
1126Floating Point
1127--------------
1128
1129 The V850 family uses IEEE floating-point numbers.
1130
1131
1132File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent
1133
1134V850 Machine Directives
1135-----------------------
1136
1137`.offset <EXPRESSION>'
1138 Moves the offset into the current section to the specified amount.
1139
1140`.section "name", <type>'
1141 This is an extension to the standard .section directive. It sets
1142 the current section to be <type> and creates an alias for this
1143 section called "name".
1144
1145`.v850'
1146 Specifies that the assembled code should be marked as being
1147 targeted at the V850 processor. This allows the linker to detect
1148 attempts to link such code with code assembled for other
1149 processors.
1150
1151`.v850e'
1152 Specifies that the assembled code should be marked as being
1153 targeted at the V850E processor. This allows the linker to detect
1154 attempts to link such code with code assembled for other
1155 processors.
1156
1157
1158File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent
1159
1160Opcodes
1161-------
1162
1163 `as' implements all the standard V850 opcodes.
1164
1165 `as' also implements the following pseudo ops:
1166
1167`hi0()'
1168 Computes the higher 16 bits of the given expression and stores it
1169 into the immediate operand field of the given instruction. For
1170 example:
1171
1172 `mulhi hi0(here - there), r5, r6'
1173
1174 computes the difference between the address of labels 'here' and
1175 'there', takes the upper 16 bits of this difference, shifts it
1176 down 16 bits and then mutliplies it by the lower 16 bits in
1177 register 5, putting the result into register 6.
1178
1179`lo()'
1180 Computes the lower 16 bits of the given expression and stores it
1181 into the immediate operand field of the given instruction. For
1182 example:
1183
1184 `addi lo(here - there), r5, r6'
1185
1186 computes the difference between the address of labels 'here' and
1187 'there', takes the lower 16 bits of this difference and adds it to
1188 register 5, putting the result into register 6.
1189
1190`hi()'
1191 Computes the higher 16 bits of the given expression and then adds
1192 the value of the most significant bit of the lower 16 bits of the
1193 expression and stores the result into the immediate operand field
1194 of the given instruction. For example the following code can be
1195 used to compute the address of the label 'here' and store it into
1196 register 6:
1197
1198 `movhi hi(here), r0, r6' `movea lo(here), r6, r6'
1199
1200 The reason for this special behaviour is that movea performs a sign
1201 extention on its immediate operand. So for example if the address
1202 of 'here' was 0xFFFFFFFF then without the special behaviour of the
1203 hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6,
1204 then the movea instruction would takes its immediate operand,
1205 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it
1206 into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E).
1207 With the hi() pseudo op adding in the top bit of the lo() pseudo
1208 op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 =
1209 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 -
1210 the right value.
1211
1212`hilo()'
1213 Computes the 32 bit value of the given expression and stores it
1214 into the immediate operand field of the given instruction (which
1215 must be a mov instruction). For example:
1216
1217 `mov hilo(here), r6'
1218
1219 computes the absolute address of label 'here' and puts the result
1220 into register 6.
1221
1222`sdaoff()'
1223 Computes the offset of the named variable from the start of the
1224 Small Data Area (whoes address is held in register 4, the GP
1225 register) and stores the result as a 16 bit signed value in the
1226 immediate operand field of the given instruction. For example:
1227
1228 `ld.w sdaoff(_a_variable)[gp],r6'
1229
1230 loads the contents of the location pointed to by the label
1231 '_a_variable' into register 6, provided that the label is located
1232 somewhere within +/- 32K of the address held in the GP register.
1233 [Note the linker assumes that the GP register contains a fixed
1234 address set to the address of the label called '__gp'. This can
1235 either be set up automatically by the linker, or specifically set
1236 by using the `--defsym __gp=<value>' command line option].
1237
1238`tdaoff()'
1239 Computes the offset of the named variable from the start of the
1240 Tiny Data Area (whoes address is held in register 30, the EP
1241 register) and stores the result as a 4,5, 7 or 8 bit unsigned
1242 value in the immediate operand field of the given instruction.
1243 For example:
1244
1245 `sld.w tdaoff(_a_variable)[ep],r6'
1246
1247 loads the contents of the location pointed to by the label
1248 '_a_variable' into register 6, provided that the label is located
1249 somewhere within +256 bytes of the address held in the EP
1250 register. [Note the linker assumes that the EP register contains
1251 a fixed address set to the address of the label called '__ep'.
1252 This can either be set up automatically by the linker, or
1253 specifically set by using the `--defsym __ep=<value>' command line
1254 option].
1255
1256`zdaoff()'
1257 Computes the offset of the named variable from address 0 and
1258 stores the result as a 16 bit signed value in the immediate
1259 operand field of the given instruction. For example:
1260
1261 `movea zdaoff(_a_variable),zero,r6'
1262
1263 puts the address of the label '_a_variable' into register 6,
1264 assuming that the label is somewhere within the first 32K of
1265 memory. (Strictly speaking it also possible to access the last
1266 32K of memory as well, as the offsets are signed).
1267
1268`ctoff()'
1269 Computes the offset of the named variable from the start of the
1270 Call Table Area (whoes address is helg in system register 20, the
1271 CTBP register) and stores the result a 6 or 16 bit unsigned value
1272 in the immediate field of then given instruction or piece of data.
1273 For example:
1274
1275 `callt ctoff(table_func1)'
1276
1277 will put the call the function whoes address is held in the call
1278 table at the location labeled 'table_func1'.
1279
1280 For information on the V850 instruction set, see `V850 Family
128132-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC.
1282Ltd.
1283
1284
1285File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top
1286
1287Reporting Bugs
1288**************
1289
1290 Your bug reports play an essential role in making `as' reliable.
1291
1292 Reporting a bug may help you by bringing a solution to your problem,
1293or it may not. But in any case the principal function of a bug report
1294is to help the entire community by making the next version of `as' work
1295better. Bug reports are your contribution to the maintenance of `as'.
1296
1297 In order for a bug report to serve its purpose, you must include the
1298information that enables us to fix the bug.
1299
1300* Menu:
1301
1302* Bug Criteria:: Have you found a bug?
1303* Bug Reporting:: How to report bugs
1304
1305
1306File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs
1307
1308Have you found a bug?
1309=====================
1310
1311 If you are not sure whether you have found a bug, here are some
1312guidelines:
1313
1314 * If the assembler gets a fatal signal, for any input whatever, that
1315 is a `as' bug. Reliable assemblers never crash.
1316
1317 * If `as' produces an error message for valid input, that is a bug.
1318
1319 * If `as' does not produce an error message for invalid input, that
1320 is a bug. However, you should note that your idea of "invalid
1321 input" might be our idea of "an extension" or "support for
1322 traditional practice".
1323
1324 * If you are an experienced user of assemblers, your suggestions for
1325 improvement of `as' are welcome in any case.
1326
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