source: trunk/src/binutils/gas/config/tc-i386.c@ 10

Last change on this file since 10 was 10, checked in by bird, 23 years ago

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1/* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001
4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus ([email protected]).
25 x86_64 support by Jan Hubicka ([email protected])
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
28
29#include <ctype.h>
30
31#include "as.h"
32#include "subsegs.h"
33#include "dwarf2dbg.h"
34#include "opcode/i386.h"
35
36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
40#ifndef INFER_ADDR_PREFIX
41#define INFER_ADDR_PREFIX 1
42#endif
43
44#ifndef SCALE1_WHEN_NO_INDEX
45/* Specifying a scale factor besides 1 when there is no index is
46 futile. eg. `mov (%ebx,2),%al' does exactly the same as
47 `mov (%ebx),%al'. To slavishly follow what the programmer
48 specified, set SCALE1_WHEN_NO_INDEX to 0. */
49#define SCALE1_WHEN_NO_INDEX 1
50#endif
51
52#define true 1
53#define false 0
54
55static unsigned int mode_from_disp_size PARAMS ((unsigned int));
56static int fits_in_signed_byte PARAMS ((offsetT));
57static int fits_in_unsigned_byte PARAMS ((offsetT));
58static int fits_in_unsigned_word PARAMS ((offsetT));
59static int fits_in_signed_word PARAMS ((offsetT));
60static int fits_in_unsigned_long PARAMS ((offsetT));
61static int fits_in_signed_long PARAMS ((offsetT));
62static int smallest_imm_type PARAMS ((offsetT));
63static offsetT offset_in_range PARAMS ((offsetT, int));
64static int add_prefix PARAMS ((unsigned int));
65static void set_code_flag PARAMS ((int));
66static void set_16bit_gcc_code_flag PARAMS ((int));
67static void set_intel_syntax PARAMS ((int));
68static void set_cpu_arch PARAMS ((int));
69
70#ifdef BFD_ASSEMBLER
71static bfd_reloc_code_real_type reloc
72 PARAMS ((int, int, int, bfd_reloc_code_real_type));
73#define RELOC_ENUM enum bfd_reloc_code_real
74#else
75#define RELOC_ENUM int
76#endif
77
78#ifndef DEFAULT_ARCH
79#define DEFAULT_ARCH "i386"
80#endif
81static char *default_arch = DEFAULT_ARCH;
82
83/* 'md_assemble ()' gathers together information and puts it into a
84 i386_insn. */
85
86union i386_op
87 {
88 expressionS *disps;
89 expressionS *imms;
90 const reg_entry *regs;
91 };
92
93struct _i386_insn
94 {
95 /* TM holds the template for the insn were currently assembling. */
96 template tm;
97
98 /* SUFFIX holds the instruction mnemonic suffix if given.
99 (e.g. 'l' for 'movl') */
100 char suffix;
101
102 /* OPERANDS gives the number of given operands. */
103 unsigned int operands;
104
105 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
106 of given register, displacement, memory operands and immediate
107 operands. */
108 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
109
110 /* TYPES [i] is the type (see above #defines) which tells us how to
111 use OP[i] for the corresponding operand. */
112 unsigned int types[MAX_OPERANDS];
113
114 /* Displacement expression, immediate expression, or register for each
115 operand. */
116 union i386_op op[MAX_OPERANDS];
117
118 /* Flags for operands. */
119 unsigned int flags[MAX_OPERANDS];
120#define Operand_PCrel 1
121
122 /* Relocation type for operand */
123 RELOC_ENUM reloc[MAX_OPERANDS];
124
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry *base_reg;
128 const reg_entry *index_reg;
129 unsigned int log2_scale_factor;
130
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry *seg[2];
134
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes;
138 unsigned char prefix[MAX_PREFIXES];
139
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
142
143 modrm_byte rm;
144 rex_byte rex;
145 sib_byte sib;
146 };
147
148typedef struct _i386_insn i386_insn;
149
150/* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
152#ifdef LEX_AT
153const char extra_symbol_chars[] = "*%-(@";
154#else
155const char extra_symbol_chars[] = "*%-(";
156#endif
157
158/* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161/* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163const char comment_chars[] = "#/";
164#define PREFIX_SEPARATOR '\\'
165#else
166const char comment_chars[] = "#";
167#define PREFIX_SEPARATOR '/'
168#endif
169
170/* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179const char line_comment_chars[] = "";
180#else
181const char line_comment_chars[] = "/";
182#endif
183
184const char line_separator_chars[] = ";";
185
186/* Chars that can be used to separate mant from exp in floating point
187 nums. */
188const char EXP_CHARS[] = "eE";
189
190/* Chars that mean this number is a floating point constant
191 As in 0f12.456
192 or 0d1.2345e12. */
193const char FLT_CHARS[] = "fFdDxX";
194
195/* Tables for lexical analysis. */
196static char mnemonic_chars[256];
197static char register_chars[256];
198static char operand_chars[256];
199static char identifier_chars[256];
200static char digit_chars[256];
201
202/* Lexical macros. */
203#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204#define is_operand_char(x) (operand_chars[(unsigned char) x])
205#define is_register_char(x) (register_chars[(unsigned char) x])
206#define is_space_char(x) ((x) == ' ')
207#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208#define is_digit_char(x) (digit_chars[(unsigned char) x])
209
210/* All non-digit non-letter charcters that may occur in an operand. */
211static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
212
213/* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217static char save_stack[32];
218static char *save_stack_p;
219#define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221#define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
223
224/* The instruction we're assembling. */
225static i386_insn i;
226
227/* Possible templates for current insn. */
228static const templates *current_templates;
229
230/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231static expressionS disp_expressions[2], im_expressions[2];
232
233/* Current operand we are working on. */
234static int this_operand;
235
236/* We support four different modes. FLAG_CODE variable is used to distinguish
237 these. */
238
239enum flag_code {
240 CODE_32BIT,
241 CODE_16BIT,
242 CODE_64BIT };
243#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
244
245static enum flag_code flag_code;
246static int use_rela_relocations = 0;
247
248/* The names used to print error messages. */
249static const char *flag_code_names[] =
250 {
251 "32",
252 "16",
253 "64"
254 };
255
256/* 1 for intel syntax,
257 0 if att syntax. */
258static int intel_syntax = 0;
259
260/* 1 if register prefix % not required. */
261static int allow_naked_reg = 0;
262
263/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
264 leave, push, and pop instructions so that gcc has the same stack
265 frame as in 32 bit mode. */
266static char stackop_size = '\0';
267
268/* Non-zero to quieten some warnings. */
269static int quiet_warnings = 0;
270
271/* CPU name. */
272static const char *cpu_arch_name = NULL;
273
274/* CPU feature flags. */
275static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64;
276
277/* If set, conditional jumps are not automatically promoted to handle
278 larger than a byte offset. */
279static unsigned int no_cond_jump_promotion = 0;
280
281/* Interface to relax_segment.
282 There are 3 major relax states for 386 jump insns because the
283 different types of jumps add different sizes to frags when we're
284 figuring out what sort of jump to choose to reach a given label. */
285
286/* Types. */
287#define UNCOND_JUMP 0
288#define COND_JUMP 1
289#define COND_JUMP86 2
290
291/* Sizes. */
292#define CODE16 1
293#define SMALL 0
294#define SMALL16 (SMALL|CODE16)
295#define BIG 2
296#define BIG16 (BIG|CODE16)
297
298#ifndef INLINE
299#ifdef __GNUC__
300#define INLINE __inline__
301#else
302#define INLINE
303#endif
304#endif
305
306#define ENCODE_RELAX_STATE(type, size) \
307 ((relax_substateT) (((type) << 2) | (size)))
308#define TYPE_FROM_RELAX_STATE(s) \
309 ((s) >> 2)
310#define DISP_SIZE_FROM_RELAX_STATE(s) \
311 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
312
313/* This table is used by relax_frag to promote short jumps to long
314 ones where necessary. SMALL (short) jumps may be promoted to BIG
315 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
316 don't allow a short jump in a 32 bit code segment to be promoted to
317 a 16 bit offset jump because it's slower (requires data size
318 prefix), and doesn't work, unless the destination is in the bottom
319 64k of the code segment (The top 16 bits of eip are zeroed). */
320
321const relax_typeS md_relax_table[] =
322{
323 /* The fields are:
324 1) most positive reach of this state,
325 2) most negative reach of this state,
326 3) how many bytes this mode will have in the variable part of the frag
327 4) which index into the table to try if we can't fit into this one. */
328
329 /* UNCOND_JUMP states. */
330 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
331 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
332 /* dword jmp adds 4 bytes to frag:
333 0 extra opcode bytes, 4 displacement bytes. */
334 {0, 0, 4, 0},
335 /* word jmp adds 2 byte2 to frag:
336 0 extra opcode bytes, 2 displacement bytes. */
337 {0, 0, 2, 0},
338
339 /* COND_JUMP states. */
340 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
341 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
342 /* dword conditionals adds 5 bytes to frag:
343 1 extra opcode byte, 4 displacement bytes. */
344 {0, 0, 5, 0},
345 /* word conditionals add 3 bytes to frag:
346 1 extra opcode byte, 2 displacement bytes. */
347 {0, 0, 3, 0},
348
349 /* COND_JUMP86 states. */
350 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
351 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
352 /* dword conditionals adds 5 bytes to frag:
353 1 extra opcode byte, 4 displacement bytes. */
354 {0, 0, 5, 0},
355 /* word conditionals add 4 bytes to frag:
356 1 displacement byte and a 3 byte long branch insn. */
357 {0, 0, 4, 0}
358};
359
360static const arch_entry cpu_arch[] = {
361 {"i8086", Cpu086 },
362 {"i186", Cpu086|Cpu186 },
363 {"i286", Cpu086|Cpu186|Cpu286 },
364 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
365 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
366 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
367 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
368 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
369 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
370 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
371 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
372 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
373 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
374 {NULL, 0 }
375};
376
377void
378i386_align_code (fragP, count)
379 fragS *fragP;
380 int count;
381{
382 /* Various efficient no-op patterns for aligning code labels.
383 Note: Don't try to assemble the instructions in the comments.
384 0L and 0w are not legal. */
385 static const char f32_1[] =
386 {0x90}; /* nop */
387 static const char f32_2[] =
388 {0x89,0xf6}; /* movl %esi,%esi */
389 static const char f32_3[] =
390 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
391 static const char f32_4[] =
392 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
393 static const char f32_5[] =
394 {0x90, /* nop */
395 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
396 static const char f32_6[] =
397 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
398 static const char f32_7[] =
399 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
400 static const char f32_8[] =
401 {0x90, /* nop */
402 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
403 static const char f32_9[] =
404 {0x89,0xf6, /* movl %esi,%esi */
405 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
406 static const char f32_10[] =
407 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
408 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
409 static const char f32_11[] =
410 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
411 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
412 static const char f32_12[] =
413 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
414 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
415 static const char f32_13[] =
416 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
417 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
418 static const char f32_14[] =
419 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
420 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
421 static const char f32_15[] =
422 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
423 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
424 static const char f16_3[] =
425 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
426 static const char f16_4[] =
427 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
428 static const char f16_5[] =
429 {0x90, /* nop */
430 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
431 static const char f16_6[] =
432 {0x89,0xf6, /* mov %si,%si */
433 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
434 static const char f16_7[] =
435 {0x8d,0x74,0x00, /* lea 0(%si),%si */
436 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
437 static const char f16_8[] =
438 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
439 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
440 static const char *const f32_patt[] = {
441 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
442 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
443 };
444 static const char *const f16_patt[] = {
445 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
446 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
447 };
448
449 /* ??? We can't use these fillers for x86_64, since they often kills the
450 upper halves. Solve later. */
451 if (flag_code == CODE_64BIT)
452 count = 1;
453
454 if (count > 0 && count <= 15)
455 {
456 if (flag_code == CODE_16BIT)
457 {
458 memcpy (fragP->fr_literal + fragP->fr_fix,
459 f16_patt[count - 1], count);
460 if (count > 8)
461 /* Adjust jump offset. */
462 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
463 }
464 else
465 memcpy (fragP->fr_literal + fragP->fr_fix,
466 f32_patt[count - 1], count);
467 fragP->fr_var = count;
468 }
469}
470
471static char *output_invalid PARAMS ((int c));
472static int i386_operand PARAMS ((char *operand_string));
473static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
474static const reg_entry *parse_register PARAMS ((char *reg_string,
475 char **end_op));
476
477#ifndef I386COFF
478static void s_bss PARAMS ((int));
479#endif
480
481symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
482
483static INLINE unsigned int
484mode_from_disp_size (t)
485 unsigned int t;
486{
487 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
488}
489
490static INLINE int
491fits_in_signed_byte (num)
492 offsetT num;
493{
494 return (num >= -128) && (num <= 127);
495}
496
497static INLINE int
498fits_in_unsigned_byte (num)
499 offsetT num;
500{
501 return (num & 0xff) == num;
502}
503
504static INLINE int
505fits_in_unsigned_word (num)
506 offsetT num;
507{
508 return (num & 0xffff) == num;
509}
510
511static INLINE int
512fits_in_signed_word (num)
513 offsetT num;
514{
515 return (-32768 <= num) && (num <= 32767);
516}
517static INLINE int
518fits_in_signed_long (num)
519 offsetT num ATTRIBUTE_UNUSED;
520{
521#ifndef BFD64
522 return 1;
523#else
524 return (!(((offsetT) -1 << 31) & num)
525 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
526#endif
527} /* fits_in_signed_long() */
528static INLINE int
529fits_in_unsigned_long (num)
530 offsetT num ATTRIBUTE_UNUSED;
531{
532#ifndef BFD64
533 return 1;
534#else
535 return (num & (((offsetT) 2 << 31) - 1)) == num;
536#endif
537} /* fits_in_unsigned_long() */
538
539static int
540smallest_imm_type (num)
541 offsetT num;
542{
543 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)
544 && !(cpu_arch_flags & (CpuUnknown)))
545 {
546 /* This code is disabled on the 486 because all the Imm1 forms
547 in the opcode table are slower on the i486. They're the
548 versions with the implicitly specified single-position
549 displacement, which has another syntax if you really want to
550 use that form. */
551 if (num == 1)
552 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
553 }
554 return (fits_in_signed_byte (num)
555 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
556 : fits_in_unsigned_byte (num)
557 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
558 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
559 ? (Imm16 | Imm32 | Imm32S | Imm64)
560 : fits_in_signed_long (num)
561 ? (Imm32 | Imm32S | Imm64)
562 : fits_in_unsigned_long (num)
563 ? (Imm32 | Imm64)
564 : Imm64);
565}
566
567static offsetT
568offset_in_range (val, size)
569 offsetT val;
570 int size;
571{
572 addressT mask;
573
574 switch (size)
575 {
576 case 1: mask = ((addressT) 1 << 8) - 1; break;
577 case 2: mask = ((addressT) 1 << 16) - 1; break;
578 case 4: mask = ((addressT) 2 << 31) - 1; break;
579#ifdef BFD64
580 case 8: mask = ((addressT) 2 << 63) - 1; break;
581#endif
582 default: abort ();
583 }
584
585 /* If BFD64, sign extend val. */
586 if (!use_rela_relocations)
587 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
588 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
589
590 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
591 {
592 char buf1[40], buf2[40];
593
594 sprint_value (buf1, val);
595 sprint_value (buf2, val & mask);
596 as_warn (_("%s shortened to %s"), buf1, buf2);
597 }
598 return val & mask;
599}
600
601/* Returns 0 if attempting to add a prefix where one from the same
602 class already exists, 1 if non rep/repne added, 2 if rep/repne
603 added. */
604static int
605add_prefix (prefix)
606 unsigned int prefix;
607{
608 int ret = 1;
609 int q;
610
611 if (prefix >= 0x40 && prefix < 0x50 && flag_code == CODE_64BIT)
612 q = REX_PREFIX;
613 else
614 switch (prefix)
615 {
616 default:
617 abort ();
618
619 case CS_PREFIX_OPCODE:
620 case DS_PREFIX_OPCODE:
621 case ES_PREFIX_OPCODE:
622 case FS_PREFIX_OPCODE:
623 case GS_PREFIX_OPCODE:
624 case SS_PREFIX_OPCODE:
625 q = SEG_PREFIX;
626 break;
627
628 case REPNE_PREFIX_OPCODE:
629 case REPE_PREFIX_OPCODE:
630 ret = 2;
631 /* fall thru */
632 case LOCK_PREFIX_OPCODE:
633 q = LOCKREP_PREFIX;
634 break;
635
636 case FWAIT_OPCODE:
637 q = WAIT_PREFIX;
638 break;
639
640 case ADDR_PREFIX_OPCODE:
641 q = ADDR_PREFIX;
642 break;
643
644 case DATA_PREFIX_OPCODE:
645 q = DATA_PREFIX;
646 break;
647 }
648
649 if (i.prefix[q])
650 {
651 as_bad (_("same type of prefix used twice"));
652 return 0;
653 }
654
655 i.prefixes += 1;
656 i.prefix[q] = prefix;
657 return ret;
658}
659
660static void
661set_code_flag (value)
662 int value;
663{
664 flag_code = value;
665 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
666 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
667 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
668 {
669 as_bad (_("64bit mode not supported on this CPU."));
670 }
671 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
672 {
673 as_bad (_("32bit mode not supported on this CPU."));
674 }
675 stackop_size = '\0';
676}
677
678static void
679set_16bit_gcc_code_flag (new_code_flag)
680 int new_code_flag;
681{
682 flag_code = new_code_flag;
683 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
684 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
685 stackop_size = 'l';
686}
687
688static void
689set_intel_syntax (syntax_flag)
690 int syntax_flag;
691{
692 /* Find out if register prefixing is specified. */
693 int ask_naked_reg = 0;
694
695 SKIP_WHITESPACE ();
696 if (! is_end_of_line[(unsigned char) *input_line_pointer])
697 {
698 char *string = input_line_pointer;
699 int e = get_symbol_end ();
700
701 if (strcmp (string, "prefix") == 0)
702 ask_naked_reg = 1;
703 else if (strcmp (string, "noprefix") == 0)
704 ask_naked_reg = -1;
705 else
706 as_bad (_("bad argument to syntax directive."));
707 *input_line_pointer = e;
708 }
709 demand_empty_rest_of_line ();
710
711 intel_syntax = syntax_flag;
712
713 if (ask_naked_reg == 0)
714 {
715#ifdef BFD_ASSEMBLER
716 allow_naked_reg = (intel_syntax
717 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
718#else
719 /* Conservative default. */
720 allow_naked_reg = 0;
721#endif
722 }
723 else
724 allow_naked_reg = (ask_naked_reg < 0);
725}
726
727static void
728set_cpu_arch (dummy)
729 int dummy ATTRIBUTE_UNUSED;
730{
731 SKIP_WHITESPACE ();
732
733 if (! is_end_of_line[(unsigned char) *input_line_pointer])
734 {
735 char *string = input_line_pointer;
736 int e = get_symbol_end ();
737 int i;
738
739 for (i = 0; cpu_arch[i].name; i++)
740 {
741 if (strcmp (string, cpu_arch[i].name) == 0)
742 {
743 cpu_arch_name = cpu_arch[i].name;
744 cpu_arch_flags = (cpu_arch[i].flags
745 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
746 break;
747 }
748 }
749 if (!cpu_arch[i].name)
750 as_bad (_("no such architecture: `%s'"), string);
751
752 *input_line_pointer = e;
753 }
754 else
755 as_bad (_("missing cpu architecture"));
756
757 no_cond_jump_promotion = 0;
758 if (*input_line_pointer == ','
759 && ! is_end_of_line[(unsigned char) input_line_pointer[1]])
760 {
761 char *string = ++input_line_pointer;
762 int e = get_symbol_end ();
763
764 if (strcmp (string, "nojumps") == 0)
765 no_cond_jump_promotion = 1;
766 else if (strcmp (string, "jumps") == 0)
767 ;
768 else
769 as_bad (_("no such architecture modifier: `%s'"), string);
770
771 *input_line_pointer = e;
772 }
773
774 demand_empty_rest_of_line ();
775}
776
777const pseudo_typeS md_pseudo_table[] =
778{
779#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
780 {"align", s_align_bytes, 0},
781#else
782 {"align", s_align_ptwo, 0},
783#endif
784 {"arch", set_cpu_arch, 0},
785#ifndef I386COFF
786 {"bss", s_bss, 0},
787#endif
788 {"ffloat", float_cons, 'f'},
789 {"dfloat", float_cons, 'd'},
790 {"tfloat", float_cons, 'x'},
791 {"value", cons, 2},
792 {"noopt", s_ignore, 0},
793 {"optim", s_ignore, 0},
794 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
795 {"code16", set_code_flag, CODE_16BIT},
796 {"code32", set_code_flag, CODE_32BIT},
797 {"code64", set_code_flag, CODE_64BIT},
798 {"intel_syntax", set_intel_syntax, 1},
799 {"att_syntax", set_intel_syntax, 0},
800 {"file", dwarf2_directive_file, 0},
801 {"loc", dwarf2_directive_loc, 0},
802 {0, 0, 0}
803};
804
805/* For interface with expression (). */
806extern char *input_line_pointer;
807
808/* Hash table for instruction mnemonic lookup. */
809static struct hash_control *op_hash;
810
811/* Hash table for register lookup. */
812static struct hash_control *reg_hash;
813
814
815#ifdef BFD_ASSEMBLER
816unsigned long
817i386_mach ()
818{
819 if (!strcmp (default_arch, "x86_64"))
820 return bfd_mach_x86_64;
821 else if (!strcmp (default_arch, "i386"))
822 return bfd_mach_i386_i386;
823 else
824 as_fatal (_("Unknown architecture"));
825}
826#endif
827
828
829void
830md_begin ()
831{
832 const char *hash_err;
833
834 /* Initialize op_hash hash table. */
835 op_hash = hash_new ();
836
837 {
838 register const template *optab;
839 register templates *core_optab;
840
841 /* Setup for loop. */
842 optab = i386_optab;
843 core_optab = (templates *) xmalloc (sizeof (templates));
844 core_optab->start = optab;
845
846 while (1)
847 {
848 ++optab;
849 if (optab->name == NULL
850 || strcmp (optab->name, (optab - 1)->name) != 0)
851 {
852 /* different name --> ship out current template list;
853 add to hash table; & begin anew. */
854 core_optab->end = optab;
855 hash_err = hash_insert (op_hash,
856 (optab - 1)->name,
857 (PTR) core_optab);
858 if (hash_err)
859 {
860 as_fatal (_("Internal Error: Can't hash %s: %s"),
861 (optab - 1)->name,
862 hash_err);
863 }
864 if (optab->name == NULL)
865 break;
866 core_optab = (templates *) xmalloc (sizeof (templates));
867 core_optab->start = optab;
868 }
869 }
870 }
871
872 /* Initialize reg_hash hash table. */
873 reg_hash = hash_new ();
874 {
875 register const reg_entry *regtab;
876
877 for (regtab = i386_regtab;
878 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
879 regtab++)
880 {
881 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
882 if (hash_err)
883 as_fatal (_("Internal Error: Can't hash %s: %s"),
884 regtab->reg_name,
885 hash_err);
886 }
887 }
888
889 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
890 {
891 register int c;
892 register char *p;
893
894 for (c = 0; c < 256; c++)
895 {
896 if (isdigit (c))
897 {
898 digit_chars[c] = c;
899 mnemonic_chars[c] = c;
900 register_chars[c] = c;
901 operand_chars[c] = c;
902 }
903 else if (islower (c))
904 {
905 mnemonic_chars[c] = c;
906 register_chars[c] = c;
907 operand_chars[c] = c;
908 }
909 else if (isupper (c))
910 {
911 mnemonic_chars[c] = tolower (c);
912 register_chars[c] = mnemonic_chars[c];
913 operand_chars[c] = c;
914 }
915
916 if (isalpha (c) || isdigit (c))
917 identifier_chars[c] = c;
918 else if (c >= 128)
919 {
920 identifier_chars[c] = c;
921 operand_chars[c] = c;
922 }
923 }
924
925#ifdef LEX_AT
926 identifier_chars['@'] = '@';
927#endif
928 digit_chars['-'] = '-';
929 identifier_chars['_'] = '_';
930 identifier_chars['.'] = '.';
931
932 for (p = operand_special_chars; *p != '\0'; p++)
933 operand_chars[(unsigned char) *p] = *p;
934 }
935
936#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
937 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
938 {
939 record_alignment (text_section, 2);
940 record_alignment (data_section, 2);
941 record_alignment (bss_section, 2);
942 }
943#endif
944}
945
946void
947i386_print_statistics (file)
948 FILE *file;
949{
950 hash_print_statistics (file, "i386 opcode", op_hash);
951 hash_print_statistics (file, "i386 register", reg_hash);
952}
953
954
955#ifdef DEBUG386
956
957/* Debugging routines for md_assemble. */
958static void pi PARAMS ((char *, i386_insn *));
959static void pte PARAMS ((template *));
960static void pt PARAMS ((unsigned int));
961static void pe PARAMS ((expressionS *));
962static void ps PARAMS ((symbolS *));
963
964static void
965pi (line, x)
966 char *line;
967 i386_insn *x;
968{
969 unsigned int i;
970
971 fprintf (stdout, "%s: template ", line);
972 pte (&x->tm);
973 fprintf (stdout, " address: base %s index %s scale %x\n",
974 x->base_reg ? x->base_reg->reg_name : "none",
975 x->index_reg ? x->index_reg->reg_name : "none",
976 x->log2_scale_factor);
977 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
978 x->rm.mode, x->rm.reg, x->rm.regmem);
979 fprintf (stdout, " sib: base %x index %x scale %x\n",
980 x->sib.base, x->sib.index, x->sib.scale);
981 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
982 x->rex.mode64, x->rex.extX, x->rex.extY, x->rex.extZ);
983 for (i = 0; i < x->operands; i++)
984 {
985 fprintf (stdout, " #%d: ", i + 1);
986 pt (x->types[i]);
987 fprintf (stdout, "\n");
988 if (x->types[i]
989 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
990 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
991 if (x->types[i] & Imm)
992 pe (x->op[i].imms);
993 if (x->types[i] & Disp)
994 pe (x->op[i].disps);
995 }
996}
997
998static void
999pte (t)
1000 template *t;
1001{
1002 unsigned int i;
1003 fprintf (stdout, " %d operands ", t->operands);
1004 fprintf (stdout, "opcode %x ", t->base_opcode);
1005 if (t->extension_opcode != None)
1006 fprintf (stdout, "ext %x ", t->extension_opcode);
1007 if (t->opcode_modifier & D)
1008 fprintf (stdout, "D");
1009 if (t->opcode_modifier & W)
1010 fprintf (stdout, "W");
1011 fprintf (stdout, "\n");
1012 for (i = 0; i < t->operands; i++)
1013 {
1014 fprintf (stdout, " #%d type ", i + 1);
1015 pt (t->operand_types[i]);
1016 fprintf (stdout, "\n");
1017 }
1018}
1019
1020static void
1021pe (e)
1022 expressionS *e;
1023{
1024 fprintf (stdout, " operation %d\n", e->X_op);
1025 fprintf (stdout, " add_number %ld (%lx)\n",
1026 (long) e->X_add_number, (long) e->X_add_number);
1027 if (e->X_add_symbol)
1028 {
1029 fprintf (stdout, " add_symbol ");
1030 ps (e->X_add_symbol);
1031 fprintf (stdout, "\n");
1032 }
1033 if (e->X_op_symbol)
1034 {
1035 fprintf (stdout, " op_symbol ");
1036 ps (e->X_op_symbol);
1037 fprintf (stdout, "\n");
1038 }
1039}
1040
1041static void
1042ps (s)
1043 symbolS *s;
1044{
1045 fprintf (stdout, "%s type %s%s",
1046 S_GET_NAME (s),
1047 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1048 segment_name (S_GET_SEGMENT (s)));
1049}
1050
1051struct type_name
1052 {
1053 unsigned int mask;
1054 char *tname;
1055 }
1056
1057type_names[] =
1058{
1059 { Reg8, "r8" },
1060 { Reg16, "r16" },
1061 { Reg32, "r32" },
1062 { Reg64, "r64" },
1063 { Imm8, "i8" },
1064 { Imm8S, "i8s" },
1065 { Imm16, "i16" },
1066 { Imm32, "i32" },
1067 { Imm32S, "i32s" },
1068 { Imm64, "i64" },
1069 { Imm1, "i1" },
1070 { BaseIndex, "BaseIndex" },
1071 { Disp8, "d8" },
1072 { Disp16, "d16" },
1073 { Disp32, "d32" },
1074 { Disp32S, "d32s" },
1075 { Disp64, "d64" },
1076 { InOutPortReg, "InOutPortReg" },
1077 { ShiftCount, "ShiftCount" },
1078 { Control, "control reg" },
1079 { Test, "test reg" },
1080 { Debug, "debug reg" },
1081 { FloatReg, "FReg" },
1082 { FloatAcc, "FAcc" },
1083 { SReg2, "SReg2" },
1084 { SReg3, "SReg3" },
1085 { Acc, "Acc" },
1086 { JumpAbsolute, "Jump Absolute" },
1087 { RegMMX, "rMMX" },
1088 { RegXMM, "rXMM" },
1089 { EsSeg, "es" },
1090 { 0, "" }
1091};
1092
1093static void
1094pt (t)
1095 unsigned int t;
1096{
1097 register struct type_name *ty;
1098
1099 for (ty = type_names; ty->mask; ty++)
1100 if (t & ty->mask)
1101 fprintf (stdout, "%s, ", ty->tname);
1102 fflush (stdout);
1103}
1104
1105#endif /* DEBUG386 */
1106
1107
1108int
1109tc_i386_force_relocation (fixp)
1110 struct fix *fixp;
1111{
1112#ifdef BFD_ASSEMBLER
1113 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1114 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1115 return 1;
1116 return 0;
1117#else
1118 /* For COFF. */
1119 return fixp->fx_r_type == 7;
1120#endif
1121}
1122
1123#ifdef BFD_ASSEMBLER
1124
1125static bfd_reloc_code_real_type
1126reloc (size, pcrel, sign, other)
1127 int size;
1128 int pcrel;
1129 int sign;
1130 bfd_reloc_code_real_type other;
1131{
1132 if (other != NO_RELOC)
1133 return other;
1134
1135 if (pcrel)
1136 {
1137 if (!sign)
1138 as_bad (_("There are no unsigned pc-relative relocations"));
1139 switch (size)
1140 {
1141 case 1: return BFD_RELOC_8_PCREL;
1142 case 2: return BFD_RELOC_16_PCREL;
1143 case 4: return BFD_RELOC_32_PCREL;
1144 }
1145 as_bad (_("can not do %d byte pc-relative relocation"), size);
1146 }
1147 else
1148 {
1149 if (sign)
1150 switch (size)
1151 {
1152 case 4: return BFD_RELOC_X86_64_32S;
1153 }
1154 else
1155 switch (size)
1156 {
1157 case 1: return BFD_RELOC_8;
1158 case 2: return BFD_RELOC_16;
1159 case 4: return BFD_RELOC_32;
1160 case 8: return BFD_RELOC_64;
1161 }
1162 as_bad (_("can not do %s %d byte relocation"),
1163 sign ? "signed" : "unsigned", size);
1164 }
1165
1166 abort ();
1167 return BFD_RELOC_NONE;
1168}
1169
1170/* Here we decide which fixups can be adjusted to make them relative to
1171 the beginning of the section instead of the symbol. Basically we need
1172 to make sure that the dynamic relocations are done correctly, so in
1173 some cases we force the original symbol to be used. */
1174
1175int
1176tc_i386_fix_adjustable (fixP)
1177 fixS *fixP;
1178{
1179#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1180 /* Prevent all adjustments to global symbols, or else dynamic
1181 linking will not work correctly. */
1182 if (S_IS_EXTERNAL (fixP->fx_addsy)
1183 || S_IS_WEAK (fixP->fx_addsy))
1184 return 0;
1185#endif
1186 /* adjust_reloc_syms doesn't know about the GOT. */
1187 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1188 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1189 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1190 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1191 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1192 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1193 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1194 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1195 return 0;
1196 return 1;
1197}
1198#else
1199#define reloc(SIZE,PCREL,SIGN,OTHER) 0
1200#define BFD_RELOC_16 0
1201#define BFD_RELOC_32 0
1202#define BFD_RELOC_16_PCREL 0
1203#define BFD_RELOC_32_PCREL 0
1204#define BFD_RELOC_386_PLT32 0
1205#define BFD_RELOC_386_GOT32 0
1206#define BFD_RELOC_386_GOTOFF 0
1207#define BFD_RELOC_X86_64_PLT32 0
1208#define BFD_RELOC_X86_64_GOT32 0
1209#define BFD_RELOC_X86_64_GOTPCREL 0
1210#endif
1211
1212static int intel_float_operand PARAMS ((char *mnemonic));
1213
1214static int
1215intel_float_operand (mnemonic)
1216 char *mnemonic;
1217{
1218 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
1219 return 2;
1220
1221 if (mnemonic[0] == 'f')
1222 return 1;
1223
1224 return 0;
1225}
1226
1227/* This is the guts of the machine-dependent assembler. LINE points to a
1228 machine dependent instruction. This function is supposed to emit
1229 the frags/bytes it assembles to. */
1230
1231void
1232md_assemble (line)
1233 char *line;
1234{
1235 /* Points to template once we've found it. */
1236 const template *t;
1237
1238 int j;
1239
1240 char mnemonic[MAX_MNEM_SIZE];
1241
1242 /* Initialize globals. */
1243 memset (&i, '\0', sizeof (i));
1244 for (j = 0; j < MAX_OPERANDS; j++)
1245 i.reloc[j] = NO_RELOC;
1246 memset (disp_expressions, '\0', sizeof (disp_expressions));
1247 memset (im_expressions, '\0', sizeof (im_expressions));
1248 save_stack_p = save_stack;
1249
1250 /* First parse an instruction mnemonic & call i386_operand for the operands.
1251 We assume that the scrubber has arranged it so that line[0] is the valid
1252 start of a (possibly prefixed) mnemonic. */
1253 {
1254 char *l = line;
1255 char *token_start = l;
1256 char *mnem_p;
1257
1258 /* Non-zero if we found a prefix only acceptable with string insns. */
1259 const char *expecting_string_instruction = NULL;
1260
1261 while (1)
1262 {
1263 mnem_p = mnemonic;
1264 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1265 {
1266 mnem_p++;
1267 if (mnem_p >= mnemonic + sizeof (mnemonic))
1268 {
1269 as_bad (_("no such instruction: `%s'"), token_start);
1270 return;
1271 }
1272 l++;
1273 }
1274 if (!is_space_char (*l)
1275 && *l != END_OF_INSN
1276 && *l != PREFIX_SEPARATOR)
1277 {
1278 as_bad (_("invalid character %s in mnemonic"),
1279 output_invalid (*l));
1280 return;
1281 }
1282 if (token_start == l)
1283 {
1284 if (*l == PREFIX_SEPARATOR)
1285 as_bad (_("expecting prefix; got nothing"));
1286 else
1287 as_bad (_("expecting mnemonic; got nothing"));
1288 return;
1289 }
1290
1291 /* Look up instruction (or prefix) via hash table. */
1292 current_templates = hash_find (op_hash, mnemonic);
1293
1294 if (*l != END_OF_INSN
1295 && (! is_space_char (*l) || l[1] != END_OF_INSN)
1296 && current_templates
1297 && (current_templates->start->opcode_modifier & IsPrefix))
1298 {
1299 /* If we are in 16-bit mode, do not allow addr16 or data16.
1300 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1301 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1302 && (((current_templates->start->opcode_modifier & Size32) != 0)
1303 ^ (flag_code == CODE_16BIT)))
1304 {
1305 as_bad (_("redundant %s prefix"),
1306 current_templates->start->name);
1307 return;
1308 }
1309 /* Add prefix, checking for repeated prefixes. */
1310 switch (add_prefix (current_templates->start->base_opcode))
1311 {
1312 case 0:
1313 return;
1314 case 2:
1315 expecting_string_instruction = current_templates->start->name;
1316 break;
1317 }
1318 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1319 token_start = ++l;
1320 }
1321 else
1322 break;
1323 }
1324
1325 if (!current_templates)
1326 {
1327 /* See if we can get a match by trimming off a suffix. */
1328 switch (mnem_p[-1])
1329 {
1330 case WORD_MNEM_SUFFIX:
1331 case BYTE_MNEM_SUFFIX:
1332 case QWORD_MNEM_SUFFIX:
1333 i.suffix = mnem_p[-1];
1334 mnem_p[-1] = '\0';
1335 current_templates = hash_find (op_hash, mnemonic);
1336 break;
1337 case SHORT_MNEM_SUFFIX:
1338 case LONG_MNEM_SUFFIX:
1339 if (!intel_syntax)
1340 {
1341 i.suffix = mnem_p[-1];
1342 mnem_p[-1] = '\0';
1343 current_templates = hash_find (op_hash, mnemonic);
1344 }
1345 break;
1346
1347 /* Intel Syntax. */
1348 case 'd':
1349 if (intel_syntax)
1350 {
1351 if (intel_float_operand (mnemonic))
1352 i.suffix = SHORT_MNEM_SUFFIX;
1353 else
1354 i.suffix = LONG_MNEM_SUFFIX;
1355 mnem_p[-1] = '\0';
1356 current_templates = hash_find (op_hash, mnemonic);
1357 }
1358 break;
1359 }
1360 if (!current_templates)
1361 {
1362 as_bad (_("no such instruction: `%s'"), token_start);
1363 return;
1364 }
1365 }
1366
1367 /* Check if instruction is supported on specified architecture. */
1368 if (cpu_arch_flags != 0)
1369 {
1370 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1371 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1372 {
1373 as_warn (_("`%s' is not supported on `%s'"),
1374 current_templates->start->name, cpu_arch_name);
1375 }
1376 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1377 {
1378 as_warn (_("use .code16 to ensure correct addressing mode"));
1379 }
1380 }
1381
1382 /* Check for rep/repne without a string instruction. */
1383 if (expecting_string_instruction
1384 && !(current_templates->start->opcode_modifier & IsString))
1385 {
1386 as_bad (_("expecting string instruction after `%s'"),
1387 expecting_string_instruction);
1388 return;
1389 }
1390
1391 /* There may be operands to parse. */
1392 if (*l != END_OF_INSN)
1393 {
1394 /* 1 if operand is pending after ','. */
1395 unsigned int expecting_operand = 0;
1396
1397 /* Non-zero if operand parens not balanced. */
1398 unsigned int paren_not_balanced;
1399
1400 do
1401 {
1402 /* Skip optional white space before operand. */
1403 if (is_space_char (*l))
1404 ++l;
1405 if (!is_operand_char (*l) && *l != END_OF_INSN)
1406 {
1407 as_bad (_("invalid character %s before operand %d"),
1408 output_invalid (*l),
1409 i.operands + 1);
1410 return;
1411 }
1412 token_start = l; /* after white space */
1413 paren_not_balanced = 0;
1414 while (paren_not_balanced || *l != ',')
1415 {
1416 if (*l == END_OF_INSN)
1417 {
1418 if (paren_not_balanced)
1419 {
1420 if (!intel_syntax)
1421 as_bad (_("unbalanced parenthesis in operand %d."),
1422 i.operands + 1);
1423 else
1424 as_bad (_("unbalanced brackets in operand %d."),
1425 i.operands + 1);
1426 return;
1427 }
1428 else
1429 break; /* we are done */
1430 }
1431 else if (!is_operand_char (*l) && !is_space_char (*l))
1432 {
1433 as_bad (_("invalid character %s in operand %d"),
1434 output_invalid (*l),
1435 i.operands + 1);
1436 return;
1437 }
1438 if (!intel_syntax)
1439 {
1440 if (*l == '(')
1441 ++paren_not_balanced;
1442 if (*l == ')')
1443 --paren_not_balanced;
1444 }
1445 else
1446 {
1447 if (*l == '[')
1448 ++paren_not_balanced;
1449 if (*l == ']')
1450 --paren_not_balanced;
1451 }
1452 l++;
1453 }
1454 if (l != token_start)
1455 { /* Yes, we've read in another operand. */
1456 unsigned int operand_ok;
1457 this_operand = i.operands++;
1458 if (i.operands > MAX_OPERANDS)
1459 {
1460 as_bad (_("spurious operands; (%d operands/instruction max)"),
1461 MAX_OPERANDS);
1462 return;
1463 }
1464 /* Now parse operand adding info to 'i' as we go along. */
1465 END_STRING_AND_SAVE (l);
1466
1467 if (intel_syntax)
1468 operand_ok =
1469 i386_intel_operand (token_start,
1470 intel_float_operand (mnemonic));
1471 else
1472 operand_ok = i386_operand (token_start);
1473
1474 RESTORE_END_STRING (l);
1475 if (!operand_ok)
1476 return;
1477 }
1478 else
1479 {
1480 if (expecting_operand)
1481 {
1482 expecting_operand_after_comma:
1483 as_bad (_("expecting operand after ','; got nothing"));
1484 return;
1485 }
1486 if (*l == ',')
1487 {
1488 as_bad (_("expecting operand before ','; got nothing"));
1489 return;
1490 }
1491 }
1492
1493 /* Now *l must be either ',' or END_OF_INSN. */
1494 if (*l == ',')
1495 {
1496 if (*++l == END_OF_INSN)
1497 {
1498 /* Just skip it, if it's \n complain. */
1499 goto expecting_operand_after_comma;
1500 }
1501 expecting_operand = 1;
1502 }
1503 }
1504 while (*l != END_OF_INSN);
1505 }
1506 }
1507
1508 /* Now we've parsed the mnemonic into a set of templates, and have the
1509 operands at hand.
1510
1511 Next, we find a template that matches the given insn,
1512 making sure the overlap of the given operands types is consistent
1513 with the template operand types. */
1514
1515#define MATCH(overlap, given, template) \
1516 ((overlap & ~JumpAbsolute) \
1517 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1518
1519 /* If given types r0 and r1 are registers they must be of the same type
1520 unless the expected operand type register overlap is null.
1521 Note that Acc in a template matches every size of reg. */
1522#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1523 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1524 ((g0) & Reg) == ((g1) & Reg) || \
1525 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1526
1527 {
1528 register unsigned int overlap0, overlap1;
1529 unsigned int overlap2;
1530 unsigned int found_reverse_match;
1531 int suffix_check;
1532
1533 /* All intel opcodes have reversed operands except for "bound" and
1534 "enter". We also don't reverse intersegment "jmp" and "call"
1535 instructions with 2 immediate operands so that the immediate segment
1536 precedes the offset, as it does when in AT&T mode. "enter" and the
1537 intersegment "jmp" and "call" instructions are the only ones that
1538 have two immediate operands. */
1539 if (intel_syntax && i.operands > 1
1540 && (strcmp (mnemonic, "bound") != 0)
1541 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1542 {
1543 union i386_op temp_op;
1544 unsigned int temp_type;
1545 RELOC_ENUM temp_reloc;
1546 int xchg1 = 0;
1547 int xchg2 = 0;
1548
1549 if (i.operands == 2)
1550 {
1551 xchg1 = 0;
1552 xchg2 = 1;
1553 }
1554 else if (i.operands == 3)
1555 {
1556 xchg1 = 0;
1557 xchg2 = 2;
1558 }
1559 temp_type = i.types[xchg2];
1560 i.types[xchg2] = i.types[xchg1];
1561 i.types[xchg1] = temp_type;
1562 temp_op = i.op[xchg2];
1563 i.op[xchg2] = i.op[xchg1];
1564 i.op[xchg1] = temp_op;
1565 temp_reloc = i.reloc[xchg2];
1566 i.reloc[xchg2] = i.reloc[xchg1];
1567 i.reloc[xchg1] = temp_reloc;
1568
1569 if (i.mem_operands == 2)
1570 {
1571 const seg_entry *temp_seg;
1572 temp_seg = i.seg[0];
1573 i.seg[0] = i.seg[1];
1574 i.seg[1] = temp_seg;
1575 }
1576 }
1577
1578 if (i.imm_operands)
1579 {
1580 /* Try to ensure constant immediates are represented in the smallest
1581 opcode possible. */
1582 char guess_suffix = 0;
1583 int op;
1584
1585 if (i.suffix)
1586 guess_suffix = i.suffix;
1587 else if (i.reg_operands)
1588 {
1589 /* Figure out a suffix from the last register operand specified.
1590 We can't do this properly yet, ie. excluding InOutPortReg,
1591 but the following works for instructions with immediates.
1592 In any case, we can't set i.suffix yet. */
1593 for (op = i.operands; --op >= 0;)
1594 if (i.types[op] & Reg)
1595 {
1596 if (i.types[op] & Reg8)
1597 guess_suffix = BYTE_MNEM_SUFFIX;
1598 else if (i.types[op] & Reg16)
1599 guess_suffix = WORD_MNEM_SUFFIX;
1600 else if (i.types[op] & Reg32)
1601 guess_suffix = LONG_MNEM_SUFFIX;
1602 else if (i.types[op] & Reg64)
1603 guess_suffix = QWORD_MNEM_SUFFIX;
1604 break;
1605 }
1606 }
1607 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1608 guess_suffix = WORD_MNEM_SUFFIX;
1609
1610 for (op = i.operands; --op >= 0;)
1611 if (i.types[op] & Imm)
1612 {
1613 switch (i.op[op].imms->X_op)
1614 {
1615 case O_constant:
1616 /* If a suffix is given, this operand may be shortened. */
1617 switch (guess_suffix)
1618 {
1619 case LONG_MNEM_SUFFIX:
1620 i.types[op] |= Imm32 | Imm64;
1621 break;
1622 case WORD_MNEM_SUFFIX:
1623 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1624 break;
1625 case BYTE_MNEM_SUFFIX:
1626 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1627 break;
1628 }
1629
1630 /* If this operand is at most 16 bits, convert it
1631 to a signed 16 bit number before trying to see
1632 whether it will fit in an even smaller size.
1633 This allows a 16-bit operand such as $0xffe0 to
1634 be recognised as within Imm8S range. */
1635 if ((i.types[op] & Imm16)
1636 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
1637 {
1638 i.op[op].imms->X_add_number =
1639 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1640 }
1641 if ((i.types[op] & Imm32)
1642 && (i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) == 0)
1643 {
1644 i.op[op].imms->X_add_number =
1645 (i.op[op].imms->X_add_number ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1646 }
1647 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
1648 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1649 if (guess_suffix == QWORD_MNEM_SUFFIX)
1650 i.types[op] &= ~Imm32;
1651 break;
1652 case O_absent:
1653 case O_register:
1654 abort ();
1655 /* Symbols and expressions. */
1656 default:
1657 /* Convert symbolic operand to proper sizes for matching. */
1658 switch (guess_suffix)
1659 {
1660 case QWORD_MNEM_SUFFIX:
1661 i.types[op] = Imm64 | Imm32S;
1662 break;
1663 case LONG_MNEM_SUFFIX:
1664 i.types[op] = Imm32 | Imm64;
1665 break;
1666 case WORD_MNEM_SUFFIX:
1667 i.types[op] = Imm16 | Imm32 | Imm64;
1668 break;
1669 break;
1670 case BYTE_MNEM_SUFFIX:
1671 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1672 break;
1673 break;
1674 }
1675 break;
1676 }
1677 }
1678 }
1679
1680 if (i.disp_operands)
1681 {
1682 /* Try to use the smallest displacement type too. */
1683 int op;
1684
1685 for (op = i.operands; --op >= 0;)
1686 if ((i.types[op] & Disp)
1687 && i.op[op].disps->X_op == O_constant)
1688 {
1689 offsetT disp = i.op[op].disps->X_add_number;
1690
1691 if (i.types[op] & Disp16)
1692 {
1693 /* We know this operand is at most 16 bits, so
1694 convert to a signed 16 bit number before trying
1695 to see whether it will fit in an even smaller
1696 size. */
1697
1698 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
1699 }
1700 else if (i.types[op] & Disp32)
1701 {
1702 /* We know this operand is at most 32 bits, so convert to a
1703 signed 32 bit number before trying to see whether it will
1704 fit in an even smaller size. */
1705 disp &= (((offsetT) 2 << 31) - 1);
1706 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1707 }
1708 if (flag_code == CODE_64BIT)
1709 {
1710 if (fits_in_signed_long (disp))
1711 i.types[op] |= Disp32S;
1712 if (fits_in_unsigned_long (disp))
1713 i.types[op] |= Disp32;
1714 }
1715 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1716 && fits_in_signed_byte (disp))
1717 i.types[op] |= Disp8;
1718 }
1719 }
1720
1721 overlap0 = 0;
1722 overlap1 = 0;
1723 overlap2 = 0;
1724 found_reverse_match = 0;
1725 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1726 ? No_bSuf
1727 : (i.suffix == WORD_MNEM_SUFFIX
1728 ? No_wSuf
1729 : (i.suffix == SHORT_MNEM_SUFFIX
1730 ? No_sSuf
1731 : (i.suffix == LONG_MNEM_SUFFIX
1732 ? No_lSuf
1733 : (i.suffix == QWORD_MNEM_SUFFIX
1734 ? No_qSuf
1735 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0))))));
1736
1737 for (t = current_templates->start;
1738 t < current_templates->end;
1739 t++)
1740 {
1741 /* Must have right number of operands. */
1742 if (i.operands != t->operands)
1743 continue;
1744
1745 /* Check the suffix, except for some instructions in intel mode. */
1746 if ((t->opcode_modifier & suffix_check)
1747 && !(intel_syntax
1748 && (t->opcode_modifier & IgnoreSize))
1749 && !(intel_syntax
1750 && t->base_opcode == 0xd9
1751 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
1752 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
1753 continue;
1754
1755 /* Do not verify operands when there are none. */
1756 else if (!t->operands)
1757 {
1758 if (t->cpu_flags & ~cpu_arch_flags)
1759 continue;
1760 /* We've found a match; break out of loop. */
1761 break;
1762 }
1763
1764 overlap0 = i.types[0] & t->operand_types[0];
1765 switch (t->operands)
1766 {
1767 case 1:
1768 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
1769 continue;
1770 break;
1771 case 2:
1772 case 3:
1773 overlap1 = i.types[1] & t->operand_types[1];
1774 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
1775 || !MATCH (overlap1, i.types[1], t->operand_types[1])
1776 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1777 t->operand_types[0],
1778 overlap1, i.types[1],
1779 t->operand_types[1]))
1780 {
1781 /* Check if other direction is valid ... */
1782 if ((t->opcode_modifier & (D|FloatD)) == 0)
1783 continue;
1784
1785 /* Try reversing direction of operands. */
1786 overlap0 = i.types[0] & t->operand_types[1];
1787 overlap1 = i.types[1] & t->operand_types[0];
1788 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
1789 || !MATCH (overlap1, i.types[1], t->operand_types[0])
1790 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1791 t->operand_types[1],
1792 overlap1, i.types[1],
1793 t->operand_types[0]))
1794 {
1795 /* Does not match either direction. */
1796 continue;
1797 }
1798 /* found_reverse_match holds which of D or FloatDR
1799 we've found. */
1800 found_reverse_match = t->opcode_modifier & (D|FloatDR);
1801 }
1802 /* Found a forward 2 operand match here. */
1803 else if (t->operands == 3)
1804 {
1805 /* Here we make use of the fact that there are no
1806 reverse match 3 operand instructions, and all 3
1807 operand instructions only need to be checked for
1808 register consistency between operands 2 and 3. */
1809 overlap2 = i.types[2] & t->operand_types[2];
1810 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
1811 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
1812 t->operand_types[1],
1813 overlap2, i.types[2],
1814 t->operand_types[2]))
1815
1816 continue;
1817 }
1818 /* Found either forward/reverse 2 or 3 operand match here:
1819 slip through to break. */
1820 }
1821 if (t->cpu_flags & ~cpu_arch_flags)
1822 {
1823 found_reverse_match = 0;
1824 continue;
1825 }
1826 /* We've found a match; break out of loop. */
1827 break;
1828 }
1829 if (t == current_templates->end)
1830 {
1831 /* We found no match. */
1832 as_bad (_("suffix or operands invalid for `%s'"),
1833 current_templates->start->name);
1834 return;
1835 }
1836
1837 if (!quiet_warnings)
1838 {
1839 if (!intel_syntax
1840 && ((i.types[0] & JumpAbsolute)
1841 != (t->operand_types[0] & JumpAbsolute)))
1842 {
1843 as_warn (_("indirect %s without `*'"), t->name);
1844 }
1845
1846 if ((t->opcode_modifier & (IsPrefix|IgnoreSize))
1847 == (IsPrefix|IgnoreSize))
1848 {
1849 /* Warn them that a data or address size prefix doesn't
1850 affect assembly of the next line of code. */
1851 as_warn (_("stand-alone `%s' prefix"), t->name);
1852 }
1853 }
1854
1855 /* Copy the template we found. */
1856 i.tm = *t;
1857 if (found_reverse_match)
1858 {
1859 /* If we found a reverse match we must alter the opcode
1860 direction bit. found_reverse_match holds bits to change
1861 (different for int & float insns). */
1862
1863 i.tm.base_opcode ^= found_reverse_match;
1864
1865 i.tm.operand_types[0] = t->operand_types[1];
1866 i.tm.operand_types[1] = t->operand_types[0];
1867 }
1868
1869 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1870 if (SYSV386_COMPAT
1871 && intel_syntax
1872 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1873 i.tm.base_opcode ^= FloatR;
1874
1875 if (i.tm.opcode_modifier & FWait)
1876 if (! add_prefix (FWAIT_OPCODE))
1877 return;
1878
1879 /* Check string instruction segment overrides. */
1880 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1881 {
1882 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
1883 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
1884 {
1885 if (i.seg[0] != NULL && i.seg[0] != &es)
1886 {
1887 as_bad (_("`%s' operand %d must use `%%es' segment"),
1888 i.tm.name,
1889 mem_op + 1);
1890 return;
1891 }
1892 /* There's only ever one segment override allowed per instruction.
1893 This instruction possibly has a legal segment override on the
1894 second operand, so copy the segment to where non-string
1895 instructions store it, allowing common code. */
1896 i.seg[0] = i.seg[1];
1897 }
1898 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
1899 {
1900 if (i.seg[1] != NULL && i.seg[1] != &es)
1901 {
1902 as_bad (_("`%s' operand %d must use `%%es' segment"),
1903 i.tm.name,
1904 mem_op + 2);
1905 return;
1906 }
1907 }
1908 }
1909
1910 if (i.reg_operands && flag_code < CODE_64BIT)
1911 {
1912 int op;
1913 for (op = i.operands; --op >= 0;)
1914 if ((i.types[op] & Reg)
1915 && (i.op[op].regs->reg_flags & (RegRex64|RegRex)))
1916 {
1917 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1918 i.op[op].regs->reg_name);
1919 return;
1920 }
1921 }
1922
1923 /* If matched instruction specifies an explicit instruction mnemonic
1924 suffix, use it. */
1925 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
1926 {
1927 if (i.tm.opcode_modifier & Size16)
1928 i.suffix = WORD_MNEM_SUFFIX;
1929 else if (i.tm.opcode_modifier & Size64)
1930 i.suffix = QWORD_MNEM_SUFFIX;
1931 else
1932 i.suffix = LONG_MNEM_SUFFIX;
1933 }
1934 else if (i.reg_operands)
1935 {
1936 /* If there's no instruction mnemonic suffix we try to invent one
1937 based on register operands. */
1938 if (!i.suffix)
1939 {
1940 /* We take i.suffix from the last register operand specified,
1941 Destination register type is more significant than source
1942 register type. */
1943 int op;
1944 for (op = i.operands; --op >= 0;)
1945 if ((i.types[op] & Reg)
1946 && !(i.tm.operand_types[op] & InOutPortReg))
1947 {
1948 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
1949 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
1950 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
1951 LONG_MNEM_SUFFIX);
1952 break;
1953 }
1954 }
1955 else if (i.suffix == BYTE_MNEM_SUFFIX)
1956 {
1957 int op;
1958 for (op = i.operands; --op >= 0;)
1959 {
1960 /* If this is an eight bit register, it's OK. If it's
1961 the 16 or 32 bit version of an eight bit register,
1962 we will just use the low portion, and that's OK too. */
1963 if (i.types[op] & Reg8)
1964 continue;
1965
1966 /* movzx and movsx should not generate this warning. */
1967 if (intel_syntax
1968 && (i.tm.base_opcode == 0xfb7
1969 || i.tm.base_opcode == 0xfb6
1970 || i.tm.base_opcode == 0x63
1971 || i.tm.base_opcode == 0xfbe
1972 || i.tm.base_opcode == 0xfbf))
1973 continue;
1974
1975 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
1976#if 0
1977 /* Check that the template allows eight bit regs
1978 This kills insns such as `orb $1,%edx', which
1979 maybe should be allowed. */
1980 && (i.tm.operand_types[op] & (Reg8|InOutPortReg))
1981#endif
1982 )
1983 {
1984 /* Prohibit these changes in the 64bit mode, since
1985 the lowering is more complicated. */
1986 if (flag_code == CODE_64BIT
1987 && (i.tm.operand_types[op] & InOutPortReg) == 0)
1988 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1989 i.op[op].regs->reg_name,
1990 i.suffix);
1991#if REGISTER_WARNINGS
1992 if (!quiet_warnings
1993 && (i.tm.operand_types[op] & InOutPortReg) == 0)
1994 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1995 (i.op[op].regs
1996 + (i.types[op] & Reg16
1997 ? REGNAM_AL - REGNAM_AX
1998 : REGNAM_AL - REGNAM_EAX))->reg_name,
1999 i.op[op].regs->reg_name,
2000 i.suffix);
2001#endif
2002 continue;
2003 }
2004 /* Any other register is bad. */
2005 if (i.types[op] & (Reg | RegMMX | RegXMM
2006 | SReg2 | SReg3
2007 | Control | Debug | Test
2008 | FloatReg | FloatAcc))
2009 {
2010 as_bad (_("`%%%s' not allowed with `%s%c'"),
2011 i.op[op].regs->reg_name,
2012 i.tm.name,
2013 i.suffix);
2014 return;
2015 }
2016 }
2017 }
2018 else if (i.suffix == LONG_MNEM_SUFFIX)
2019 {
2020 int op;
2021
2022 for (op = i.operands; --op >= 0;)
2023 /* Reject eight bit registers, except where the template
2024 requires them. (eg. movzb) */
2025 if ((i.types[op] & Reg8) != 0
2026 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2027 {
2028 as_bad (_("`%%%s' not allowed with `%s%c'"),
2029 i.op[op].regs->reg_name,
2030 i.tm.name,
2031 i.suffix);
2032 return;
2033 }
2034 /* Warn if the e prefix on a general reg is missing. */
2035 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2036 && (i.types[op] & Reg16) != 0
2037 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2038 {
2039 /* Prohibit these changes in the 64bit mode, since
2040 the lowering is more complicated. */
2041 if (flag_code == CODE_64BIT)
2042 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2043 i.op[op].regs->reg_name,
2044 i.suffix);
2045#if REGISTER_WARNINGS
2046 else
2047 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2048 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2049 i.op[op].regs->reg_name,
2050 i.suffix);
2051#endif
2052 }
2053 /* Warn if the r prefix on a general reg is missing. */
2054 else if ((i.types[op] & Reg64) != 0
2055 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2056 {
2057 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2058 i.op[op].regs->reg_name,
2059 i.suffix);
2060 }
2061 }
2062 else if (i.suffix == QWORD_MNEM_SUFFIX)
2063 {
2064 int op;
2065
2066 for (op = i.operands; --op >= 0; )
2067 /* Reject eight bit registers, except where the template
2068 requires them. (eg. movzb) */
2069 if ((i.types[op] & Reg8) != 0
2070 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
2071 {
2072 as_bad (_("`%%%s' not allowed with `%s%c'"),
2073 i.op[op].regs->reg_name,
2074 i.tm.name,
2075 i.suffix);
2076 return;
2077 }
2078 /* Warn if the e prefix on a general reg is missing. */
2079 else if (((i.types[op] & Reg16) != 0
2080 || (i.types[op] & Reg32) != 0)
2081 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2082 {
2083 /* Prohibit these changes in the 64bit mode, since
2084 the lowering is more complicated. */
2085 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2086 i.op[op].regs->reg_name,
2087 i.suffix);
2088 }
2089 }
2090 else if (i.suffix == WORD_MNEM_SUFFIX)
2091 {
2092 int op;
2093 for (op = i.operands; --op >= 0;)
2094 /* Reject eight bit registers, except where the template
2095 requires them. (eg. movzb) */
2096 if ((i.types[op] & Reg8) != 0
2097 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
2098 {
2099 as_bad (_("`%%%s' not allowed with `%s%c'"),
2100 i.op[op].regs->reg_name,
2101 i.tm.name,
2102 i.suffix);
2103 return;
2104 }
2105 /* Warn if the e prefix on a general reg is present. */
2106 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2107 && (i.types[op] & Reg32) != 0
2108 && (i.tm.operand_types[op] & (Reg16|Acc)) != 0)
2109 {
2110 /* Prohibit these changes in the 64bit mode, since
2111 the lowering is more complicated. */
2112 if (flag_code == CODE_64BIT)
2113 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2114 i.op[op].regs->reg_name,
2115 i.suffix);
2116 else
2117#if REGISTER_WARNINGS
2118 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2119 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2120 i.op[op].regs->reg_name,
2121 i.suffix);
2122#endif
2123 }
2124 }
2125 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2126 /* Do nothing if the instruction is going to ignore the prefix. */
2127 ;
2128 else
2129 abort ();
2130 }
2131 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2132 {
2133 i.suffix = stackop_size;
2134 }
2135 /* Make still unresolved immediate matches conform to size of immediate
2136 given in i.suffix. Note: overlap2 cannot be an immediate! */
2137 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2138 && overlap0 != Imm8 && overlap0 != Imm8S
2139 && overlap0 != Imm16 && overlap0 != Imm32S
2140 && overlap0 != Imm32 && overlap0 != Imm64)
2141 {
2142 if (i.suffix)
2143 {
2144 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
2145 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
2146 (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
2147 }
2148 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2149 || overlap0 == (Imm16 | Imm32)
2150 || overlap0 == (Imm16 | Imm32S))
2151 {
2152 overlap0 =
2153 ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
2154 }
2155 if (overlap0 != Imm8 && overlap0 != Imm8S
2156 && overlap0 != Imm16 && overlap0 != Imm32S
2157 && overlap0 != Imm32 && overlap0 != Imm64)
2158 {
2159 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2160 return;
2161 }
2162 }
2163 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2164 && overlap1 != Imm8 && overlap1 != Imm8S
2165 && overlap1 != Imm16 && overlap1 != Imm32S
2166 && overlap1 != Imm32 && overlap1 != Imm64)
2167 {
2168 if (i.suffix)
2169 {
2170 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
2171 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
2172 (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
2173 }
2174 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2175 || overlap1 == (Imm16 | Imm32)
2176 || overlap1 == (Imm16 | Imm32S))
2177 {
2178 overlap1 =
2179 ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
2180 }
2181 if (overlap1 != Imm8 && overlap1 != Imm8S
2182 && overlap1 != Imm16 && overlap1 != Imm32S
2183 && overlap1 != Imm32 && overlap1 != Imm64)
2184 {
2185 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2186 return;
2187 }
2188 }
2189 assert ((overlap2 & Imm) == 0);
2190
2191 i.types[0] = overlap0;
2192 if (overlap0 & ImplicitRegister)
2193 i.reg_operands--;
2194 if (overlap0 & Imm1)
2195 i.imm_operands = 0; /* kludge for shift insns. */
2196
2197 i.types[1] = overlap1;
2198 if (overlap1 & ImplicitRegister)
2199 i.reg_operands--;
2200
2201 i.types[2] = overlap2;
2202 if (overlap2 & ImplicitRegister)
2203 i.reg_operands--;
2204
2205 /* Finalize opcode. First, we change the opcode based on the operand
2206 size given by i.suffix: We need not change things for byte insns. */
2207
2208 if (!i.suffix && (i.tm.opcode_modifier & W))
2209 {
2210 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2211 return;
2212 }
2213
2214 /* For movzx and movsx, need to check the register type. */
2215 if (intel_syntax
2216 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe))
2217 if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX)
2218 {
2219 unsigned int prefix = DATA_PREFIX_OPCODE;
2220
2221 if ((i.op[1].regs->reg_type & Reg16) != 0)
2222 if (!add_prefix (prefix))
2223 return;
2224 }
2225
2226 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2227 {
2228 /* It's not a byte, select word/dword operation. */
2229 if (i.tm.opcode_modifier & W)
2230 {
2231 if (i.tm.opcode_modifier & ShortForm)
2232 i.tm.base_opcode |= 8;
2233 else
2234 i.tm.base_opcode |= 1;
2235 }
2236 /* Now select between word & dword operations via the operand
2237 size prefix, except for instructions that will ignore this
2238 prefix anyway. */
2239 if (i.suffix != QWORD_MNEM_SUFFIX
2240 && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2241 && !(i.tm.opcode_modifier & IgnoreSize))
2242 {
2243 unsigned int prefix = DATA_PREFIX_OPCODE;
2244 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2245 prefix = ADDR_PREFIX_OPCODE;
2246
2247 if (! add_prefix (prefix))
2248 return;
2249 }
2250
2251 /* Set mode64 for an operand. */
2252 if (i.suffix == QWORD_MNEM_SUFFIX
2253 && !(i.tm.opcode_modifier & NoRex64))
2254 {
2255 i.rex.mode64 = 1;
2256 if (flag_code < CODE_64BIT)
2257 {
2258 as_bad (_("64bit operations available only in 64bit modes."));
2259 return;
2260 }
2261 }
2262
2263 /* Size floating point instruction. */
2264 if (i.suffix == LONG_MNEM_SUFFIX)
2265 {
2266 if (i.tm.opcode_modifier & FloatMF)
2267 i.tm.base_opcode ^= 4;
2268 }
2269 }
2270
2271 if (i.tm.opcode_modifier & ImmExt)
2272 {
2273 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2274 opcode suffix which is coded in the same place as an 8-bit
2275 immediate field would be. Here we fake an 8-bit immediate
2276 operand from the opcode suffix stored in tm.extension_opcode. */
2277
2278 expressionS *exp;
2279
2280 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
2281
2282 exp = &im_expressions[i.imm_operands++];
2283 i.op[i.operands].imms = exp;
2284 i.types[i.operands++] = Imm8;
2285 exp->X_op = O_constant;
2286 exp->X_add_number = i.tm.extension_opcode;
2287 i.tm.extension_opcode = None;
2288 }
2289
2290 /* For insns with operands there are more diddles to do to the opcode. */
2291 if (i.operands)
2292 {
2293 /* Default segment register this instruction will use
2294 for memory accesses. 0 means unknown.
2295 This is only for optimizing out unnecessary segment overrides. */
2296 const seg_entry *default_seg = 0;
2297
2298 /* The imul $imm, %reg instruction is converted into
2299 imul $imm, %reg, %reg, and the clr %reg instruction
2300 is converted into xor %reg, %reg. */
2301 if (i.tm.opcode_modifier & regKludge)
2302 {
2303 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2304 /* Pretend we saw the extra register operand. */
2305 assert (i.op[first_reg_op + 1].regs == 0);
2306 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2307 i.types[first_reg_op + 1] = i.types[first_reg_op];
2308 i.reg_operands = 2;
2309 }
2310
2311 if (i.tm.opcode_modifier & ShortForm)
2312 {
2313 /* The register or float register operand is in operand 0 or 1. */
2314 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2315 /* Register goes in low 3 bits of opcode. */
2316 i.tm.base_opcode |= i.op[op].regs->reg_num;
2317 if (i.op[op].regs->reg_flags & RegRex)
2318 i.rex.extZ = 1;
2319 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2320 {
2321 /* Warn about some common errors, but press on regardless.
2322 The first case can be generated by gcc (<= 2.8.1). */
2323 if (i.operands == 2)
2324 {
2325 /* Reversed arguments on faddp, fsubp, etc. */
2326 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2327 i.op[1].regs->reg_name,
2328 i.op[0].regs->reg_name);
2329 }
2330 else
2331 {
2332 /* Extraneous `l' suffix on fp insn. */
2333 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2334 i.op[0].regs->reg_name);
2335 }
2336 }
2337 }
2338 else if (i.tm.opcode_modifier & Modrm)
2339 {
2340 /* The opcode is completed (modulo i.tm.extension_opcode which
2341 must be put into the modrm byte).
2342 Now, we make the modrm & index base bytes based on all the
2343 info we've collected. */
2344
2345 /* i.reg_operands MUST be the number of real register operands;
2346 implicit registers do not count. */
2347 if (i.reg_operands == 2)
2348 {
2349 unsigned int source, dest;
2350 source = ((i.types[0]
2351 & (Reg | RegMMX | RegXMM
2352 | SReg2 | SReg3
2353 | Control | Debug | Test))
2354 ? 0 : 1);
2355 dest = source + 1;
2356
2357 i.rm.mode = 3;
2358 /* One of the register operands will be encoded in the
2359 i.tm.reg field, the other in the combined i.tm.mode
2360 and i.tm.regmem fields. If no form of this
2361 instruction supports a memory destination operand,
2362 then we assume the source operand may sometimes be
2363 a memory operand and so we need to store the
2364 destination in the i.rm.reg field. */
2365 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2366 {
2367 i.rm.reg = i.op[dest].regs->reg_num;
2368 i.rm.regmem = i.op[source].regs->reg_num;
2369 if (i.op[dest].regs->reg_flags & RegRex)
2370 i.rex.extX = 1;
2371 if (i.op[source].regs->reg_flags & RegRex)
2372 i.rex.extZ = 1;
2373 }
2374 else
2375 {
2376 i.rm.reg = i.op[source].regs->reg_num;
2377 i.rm.regmem = i.op[dest].regs->reg_num;
2378 if (i.op[dest].regs->reg_flags & RegRex)
2379 i.rex.extZ = 1;
2380 if (i.op[source].regs->reg_flags & RegRex)
2381 i.rex.extX = 1;
2382 }
2383 }
2384 else
2385 { /* If it's not 2 reg operands... */
2386 if (i.mem_operands)
2387 {
2388 unsigned int fake_zero_displacement = 0;
2389 unsigned int op = ((i.types[0] & AnyMem)
2390 ? 0
2391 : (i.types[1] & AnyMem) ? 1 : 2);
2392
2393 default_seg = &ds;
2394
2395 if (! i.base_reg)
2396 {
2397 i.rm.mode = 0;
2398 if (! i.disp_operands)
2399 fake_zero_displacement = 1;
2400 if (! i.index_reg)
2401 {
2402 /* Operand is just <disp> */
2403 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
2404 {
2405 i.rm.regmem = NO_BASE_REGISTER_16;
2406 i.types[op] &= ~Disp;
2407 i.types[op] |= Disp16;
2408 }
2409 else if (flag_code != CODE_64BIT)
2410 {
2411 i.rm.regmem = NO_BASE_REGISTER;
2412 i.types[op] &= ~Disp;
2413 i.types[op] |= Disp32;
2414 }
2415 else
2416 {
2417 /* 64bit mode overwrites the 32bit
2418 absolute addressing by RIP relative
2419 addressing and absolute addressing
2420 is encoded by one of the redundant
2421 SIB forms. */
2422
2423 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2424 i.sib.base = NO_BASE_REGISTER;
2425 i.sib.index = NO_INDEX_REGISTER;
2426 i.types[op] &= ~Disp;
2427 i.types[op] |= Disp32S;
2428 }
2429 }
2430 else /* ! i.base_reg && i.index_reg */
2431 {
2432 i.sib.index = i.index_reg->reg_num;
2433 i.sib.base = NO_BASE_REGISTER;
2434 i.sib.scale = i.log2_scale_factor;
2435 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2436 i.types[op] &= ~Disp;
2437 if (flag_code != CODE_64BIT)
2438 i.types[op] |= Disp32; /* Must be 32 bit */
2439 else
2440 i.types[op] |= Disp32S;
2441 if (i.index_reg->reg_flags & RegRex)
2442 i.rex.extY = 1;
2443 }
2444 }
2445 /* RIP addressing for 64bit mode. */
2446 else if (i.base_reg->reg_type == BaseIndex)
2447 {
2448 i.rm.regmem = NO_BASE_REGISTER;
2449 i.types[op] &= ~Disp;
2450 i.types[op] |= Disp32S;
2451 i.flags[op] = Operand_PCrel;
2452 }
2453 else if (i.base_reg->reg_type & Reg16)
2454 {
2455 switch (i.base_reg->reg_num)
2456 {
2457 case 3: /* (%bx) */
2458 if (! i.index_reg)
2459 i.rm.regmem = 7;
2460 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2461 i.rm.regmem = i.index_reg->reg_num - 6;
2462 break;
2463 case 5: /* (%bp) */
2464 default_seg = &ss;
2465 if (! i.index_reg)
2466 {
2467 i.rm.regmem = 6;
2468 if ((i.types[op] & Disp) == 0)
2469 {
2470 /* fake (%bp) into 0(%bp) */
2471 i.types[op] |= Disp8;
2472 fake_zero_displacement = 1;
2473 }
2474 }
2475 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2476 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2477 break;
2478 default: /* (%si) -> 4 or (%di) -> 5 */
2479 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2480 }
2481 i.rm.mode = mode_from_disp_size (i.types[op]);
2482 }
2483 else /* i.base_reg and 32/64 bit mode */
2484 {
2485 if (flag_code == CODE_64BIT
2486 && (i.types[op] & Disp))
2487 {
2488 if (i.types[op] & Disp8)
2489 i.types[op] = Disp8 | Disp32S;
2490 else
2491 i.types[op] = Disp32S;
2492 }
2493 i.rm.regmem = i.base_reg->reg_num;
2494 if (i.base_reg->reg_flags & RegRex)
2495 i.rex.extZ = 1;
2496 i.sib.base = i.base_reg->reg_num;
2497 /* x86-64 ignores REX prefix bit here to avoid
2498 decoder complications. */
2499 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2500 {
2501 default_seg = &ss;
2502 if (i.disp_operands == 0)
2503 {
2504 fake_zero_displacement = 1;
2505 i.types[op] |= Disp8;
2506 }
2507 }
2508 else if (i.base_reg->reg_num == ESP_REG_NUM)
2509 {
2510 default_seg = &ss;
2511 }
2512 i.sib.scale = i.log2_scale_factor;
2513 if (! i.index_reg)
2514 {
2515 /* <disp>(%esp) becomes two byte modrm
2516 with no index register. We've already
2517 stored the code for esp in i.rm.regmem
2518 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2519 base register besides %esp will not use
2520 the extra modrm byte. */
2521 i.sib.index = NO_INDEX_REGISTER;
2522#if ! SCALE1_WHEN_NO_INDEX
2523 /* Another case where we force the second
2524 modrm byte. */
2525 if (i.log2_scale_factor)
2526 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2527#endif
2528 }
2529 else
2530 {
2531 i.sib.index = i.index_reg->reg_num;
2532 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2533 if (i.index_reg->reg_flags & RegRex)
2534 i.rex.extY = 1;
2535 }
2536 i.rm.mode = mode_from_disp_size (i.types[op]);
2537 }
2538
2539 if (fake_zero_displacement)
2540 {
2541 /* Fakes a zero displacement assuming that i.types[op]
2542 holds the correct displacement size. */
2543 expressionS *exp;
2544
2545 assert (i.op[op].disps == 0);
2546 exp = &disp_expressions[i.disp_operands++];
2547 i.op[op].disps = exp;
2548 exp->X_op = O_constant;
2549 exp->X_add_number = 0;
2550 exp->X_add_symbol = (symbolS *) 0;
2551 exp->X_op_symbol = (symbolS *) 0;
2552 }
2553 }
2554
2555 /* Fill in i.rm.reg or i.rm.regmem field with register
2556 operand (if any) based on i.tm.extension_opcode.
2557 Again, we must be careful to make sure that
2558 segment/control/debug/test/MMX registers are coded
2559 into the i.rm.reg field. */
2560 if (i.reg_operands)
2561 {
2562 unsigned int op =
2563 ((i.types[0]
2564 & (Reg | RegMMX | RegXMM
2565 | SReg2 | SReg3
2566 | Control | Debug | Test))
2567 ? 0
2568 : ((i.types[1]
2569 & (Reg | RegMMX | RegXMM
2570 | SReg2 | SReg3
2571 | Control | Debug | Test))
2572 ? 1
2573 : 2));
2574 /* If there is an extension opcode to put here, the
2575 register number must be put into the regmem field. */
2576 if (i.tm.extension_opcode != None)
2577 {
2578 i.rm.regmem = i.op[op].regs->reg_num;
2579 if (i.op[op].regs->reg_flags & RegRex)
2580 i.rex.extZ = 1;
2581 }
2582 else
2583 {
2584 i.rm.reg = i.op[op].regs->reg_num;
2585 if (i.op[op].regs->reg_flags & RegRex)
2586 i.rex.extX = 1;
2587 }
2588
2589 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2590 we must set it to 3 to indicate this is a register
2591 operand in the regmem field. */
2592 if (!i.mem_operands)
2593 i.rm.mode = 3;
2594 }
2595
2596 /* Fill in i.rm.reg field with extension opcode (if any). */
2597 if (i.tm.extension_opcode != None)
2598 i.rm.reg = i.tm.extension_opcode;
2599 }
2600 }
2601 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2602 {
2603 if (i.tm.base_opcode == POP_SEG_SHORT
2604 && i.op[0].regs->reg_num == 1)
2605 {
2606 as_bad (_("you can't `pop %%cs'"));
2607 return;
2608 }
2609 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2610 if (i.op[0].regs->reg_flags & RegRex)
2611 i.rex.extZ = 1;
2612 }
2613 else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32)
2614 {
2615 default_seg = &ds;
2616 }
2617 else if ((i.tm.opcode_modifier & IsString) != 0)
2618 {
2619 /* For the string instructions that allow a segment override
2620 on one of their operands, the default segment is ds. */
2621 default_seg = &ds;
2622 }
2623
2624 /* If a segment was explicitly specified,
2625 and the specified segment is not the default,
2626 use an opcode prefix to select it.
2627 If we never figured out what the default segment is,
2628 then default_seg will be zero at this point,
2629 and the specified segment prefix will always be used. */
2630 if ((i.seg[0]) && (i.seg[0] != default_seg))
2631 {
2632 if (! add_prefix (i.seg[0]->seg_prefix))
2633 return;
2634 }
2635 }
2636 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2637 {
2638 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2639 as_warn (_("translating to `%sp'"), i.tm.name);
2640 }
2641 }
2642
2643 /* Handle conversion of 'int $3' --> special int3 insn. */
2644 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2645 {
2646 i.tm.base_opcode = INT3_OPCODE;
2647 i.imm_operands = 0;
2648 }
2649
2650 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
2651 && i.op[0].disps->X_op == O_constant)
2652 {
2653 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2654 the absolute address given by the constant. Since ix86 jumps and
2655 calls are pc relative, we need to generate a reloc. */
2656 i.op[0].disps->X_add_symbol = &abs_symbol;
2657 i.op[0].disps->X_op = O_symbol;
2658 }
2659
2660 if (i.tm.opcode_modifier & Rex64)
2661 i.rex.mode64 = 1;
2662
2663 /* For 8bit registers we would need an empty rex prefix.
2664 Also in the case instruction is already having prefix,
2665 we need to convert old registers to new ones. */
2666
2667 if (((i.types[0] & Reg8) && (i.op[0].regs->reg_flags & RegRex64))
2668 || ((i.types[1] & Reg8) && (i.op[1].regs->reg_flags & RegRex64))
2669 || ((i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
2670 && ((i.types[0] & Reg8) || (i.types[1] & Reg8))))
2671 {
2672 int x;
2673 i.rex.empty = 1;
2674 for (x = 0; x < 2; x++)
2675 {
2676 /* Look for 8bit operand that does use old registers. */
2677 if (i.types[x] & Reg8
2678 && !(i.op[x].regs->reg_flags & RegRex64))
2679 {
2680 /* In case it is "hi" register, give up. */
2681 if (i.op[x].regs->reg_num > 3)
2682 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2683 i.op[x].regs->reg_name);
2684
2685 /* Otherwise it is equivalent to the extended register.
2686 Since the encoding don't change this is merely cosmetical
2687 cleanup for debug output. */
2688
2689 i.op[x].regs = i.op[x].regs + 8;
2690 }
2691 }
2692 }
2693
2694 if (i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
2695 add_prefix (0x40
2696 | (i.rex.mode64 ? 8 : 0)
2697 | (i.rex.extX ? 4 : 0)
2698 | (i.rex.extY ? 2 : 0)
2699 | (i.rex.extZ ? 1 : 0));
2700
2701 /* We are ready to output the insn. */
2702 {
2703 register char *p;
2704
2705 /* Tie dwarf2 debug info to the address at the start of the insn.
2706 We can't do this after the insn has been output as the current
2707 frag may have been closed off. eg. by frag_var. */
2708 dwarf2_emit_insn (0);
2709
2710 /* Output jumps. */
2711 if (i.tm.opcode_modifier & Jump)
2712 {
2713 int code16;
2714 int prefix;
2715
2716 code16 = 0;
2717 if (flag_code == CODE_16BIT)
2718 code16 = CODE16;
2719
2720 prefix = 0;
2721 if (i.prefix[DATA_PREFIX])
2722 {
2723 prefix = 1;
2724 i.prefixes -= 1;
2725 code16 ^= CODE16;
2726 }
2727 /* Pentium4 branch hints. */
2728 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2729 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2730 {
2731 prefix++;
2732 i.prefixes--;
2733 }
2734 if (i.prefix[REX_PREFIX])
2735 {
2736 prefix++;
2737 i.prefixes--;
2738 }
2739
2740 if (i.prefixes != 0 && !intel_syntax)
2741 as_warn (_("skipping prefixes on this instruction"));
2742
2743 /* It's always a symbol; End frag & setup for relax.
2744 Make sure there is enough room in this frag for the largest
2745 instruction we may generate in md_convert_frag. This is 2
2746 bytes for the opcode and room for the prefix and largest
2747 displacement. */
2748 frag_grow (prefix + 2 + 4);
2749 /* Prefix and 1 opcode byte go in fr_fix. */
2750 p = frag_more (prefix + 1);
2751 if (i.prefix[DATA_PREFIX])
2752 *p++ = DATA_PREFIX_OPCODE;
2753 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2754 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2755 *p++ = i.prefix[SEG_PREFIX];
2756 if (i.prefix[REX_PREFIX])
2757 *p++ = i.prefix[REX_PREFIX];
2758 *p = i.tm.base_opcode;
2759 /* 1 possible extra opcode + displacement go in var part.
2760 Pass reloc in fr_var. */
2761 frag_var (rs_machine_dependent,
2762 1 + 4,
2763 i.reloc[0],
2764 ((unsigned char) *p == JUMP_PC_RELATIVE
2765 ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16
2766 : ((cpu_arch_flags & Cpu386) != 0
2767 ? ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16
2768 : ENCODE_RELAX_STATE (COND_JUMP86, SMALL) | code16)),
2769 i.op[0].disps->X_add_symbol,
2770 i.op[0].disps->X_add_number,
2771 p);
2772 }
2773 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
2774 {
2775 int size;
2776
2777 if (i.tm.opcode_modifier & JumpByte)
2778 {
2779 /* This is a loop or jecxz type instruction. */
2780 size = 1;
2781 if (i.prefix[ADDR_PREFIX])
2782 {
2783 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2784 i.prefixes -= 1;
2785 }
2786 /* Pentium4 branch hints. */
2787 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2788 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2789 {
2790 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
2791 i.prefixes--;
2792 }
2793 }
2794 else
2795 {
2796 int code16;
2797
2798 code16 = 0;
2799 if (flag_code == CODE_16BIT)
2800 code16 = CODE16;
2801
2802 if (i.prefix[DATA_PREFIX])
2803 {
2804 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
2805 i.prefixes -= 1;
2806 code16 ^= CODE16;
2807 }
2808
2809 size = 4;
2810 if (code16)
2811 size = 2;
2812 }
2813
2814 if (i.prefix[REX_PREFIX])
2815 {
2816 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
2817 i.prefixes -= 1;
2818 }
2819
2820 if (i.prefixes != 0 && !intel_syntax)
2821 as_warn (_("skipping prefixes on this instruction"));
2822
2823 p = frag_more (1 + size);
2824 *p++ = i.tm.base_opcode;
2825
2826 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2827 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
2828 }
2829 else if (i.tm.opcode_modifier & JumpInterSegment)
2830 {
2831 int size;
2832 int prefix;
2833 int code16;
2834
2835 code16 = 0;
2836 if (flag_code == CODE_16BIT)
2837 code16 = CODE16;
2838
2839 prefix = 0;
2840 if (i.prefix[DATA_PREFIX])
2841 {
2842 prefix = 1;
2843 i.prefixes -= 1;
2844 code16 ^= CODE16;
2845 }
2846 if (i.prefix[REX_PREFIX])
2847 {
2848 prefix++;
2849 i.prefixes -= 1;
2850 }
2851
2852 size = 4;
2853 if (code16)
2854 size = 2;
2855
2856 if (i.prefixes != 0 && !intel_syntax)
2857 as_warn (_("skipping prefixes on this instruction"));
2858
2859 /* 1 opcode; 2 segment; offset */
2860 p = frag_more (prefix + 1 + 2 + size);
2861
2862 if (i.prefix[DATA_PREFIX])
2863 *p++ = DATA_PREFIX_OPCODE;
2864
2865 if (i.prefix[REX_PREFIX])
2866 *p++ = i.prefix[REX_PREFIX];
2867
2868 *p++ = i.tm.base_opcode;
2869 if (i.op[1].imms->X_op == O_constant)
2870 {
2871 offsetT n = i.op[1].imms->X_add_number;
2872
2873 if (size == 2
2874 && !fits_in_unsigned_word (n)
2875 && !fits_in_signed_word (n))
2876 {
2877 as_bad (_("16-bit jump out of range"));
2878 return;
2879 }
2880 md_number_to_chars (p, n, size);
2881 }
2882 else
2883 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2884 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
2885 if (i.op[0].imms->X_op != O_constant)
2886 as_bad (_("can't handle non absolute segment in `%s'"),
2887 i.tm.name);
2888 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
2889 }
2890 else
2891 {
2892 /* Output normal instructions here. */
2893 unsigned char *q;
2894
2895 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2896 byte for the SSE instructions to specify prefix they require. */
2897 if (i.tm.base_opcode & 0xff0000)
2898 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
2899
2900 /* The prefix bytes. */
2901 for (q = i.prefix;
2902 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
2903 q++)
2904 {
2905 if (*q)
2906 {
2907 p = frag_more (1);
2908 md_number_to_chars (p, (valueT) *q, 1);
2909 }
2910 }
2911
2912 /* Now the opcode; be careful about word order here! */
2913 if (fits_in_unsigned_byte (i.tm.base_opcode))
2914 {
2915 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
2916 }
2917 else
2918 {
2919 p = frag_more (2);
2920 /* Put out high byte first: can't use md_number_to_chars! */
2921 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2922 *p = i.tm.base_opcode & 0xff;
2923 }
2924
2925 /* Now the modrm byte and sib byte (if present). */
2926 if (i.tm.opcode_modifier & Modrm)
2927 {
2928 p = frag_more (1);
2929 md_number_to_chars (p,
2930 (valueT) (i.rm.regmem << 0
2931 | i.rm.reg << 3
2932 | i.rm.mode << 6),
2933 1);
2934 /* If i.rm.regmem == ESP (4)
2935 && i.rm.mode != (Register mode)
2936 && not 16 bit
2937 ==> need second modrm byte. */
2938 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
2939 && i.rm.mode != 3
2940 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
2941 {
2942 p = frag_more (1);
2943 md_number_to_chars (p,
2944 (valueT) (i.sib.base << 0
2945 | i.sib.index << 3
2946 | i.sib.scale << 6),
2947 1);
2948 }
2949 }
2950
2951 if (i.disp_operands)
2952 {
2953 register unsigned int n;
2954
2955 for (n = 0; n < i.operands; n++)
2956 {
2957 if (i.types[n] & Disp)
2958 {
2959 if (i.op[n].disps->X_op == O_constant)
2960 {
2961 int size;
2962 offsetT val;
2963
2964 size = 4;
2965 if (i.types[n] & (Disp8 | Disp16 | Disp64))
2966 {
2967 size = 2;
2968 if (i.types[n] & Disp8)
2969 size = 1;
2970 if (i.types[n] & Disp64)
2971 size = 8;
2972 }
2973 val = offset_in_range (i.op[n].disps->X_add_number,
2974 size);
2975 p = frag_more (size);
2976 md_number_to_chars (p, val, size);
2977 }
2978 else
2979 {
2980 int size = 4;
2981 int sign = 0;
2982 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
2983
2984 /* The PC relative address is computed relative
2985 to the instruction boundary, so in case immediate
2986 fields follows, we need to adjust the value. */
2987 if (pcrel && i.imm_operands)
2988 {
2989 int imm_size = 4;
2990 register unsigned int n1;
2991
2992 for (n1 = 0; n1 < i.operands; n1++)
2993 if (i.types[n1] & Imm)
2994 {
2995 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
2996 {
2997 imm_size = 2;
2998 if (i.types[n1] & (Imm8 | Imm8S))
2999 imm_size = 1;
3000 if (i.types[n1] & Imm64)
3001 imm_size = 8;
3002 }
3003 break;
3004 }
3005 /* We should find the immediate. */
3006 if (n1 == i.operands)
3007 abort ();
3008 i.op[n].disps->X_add_number -= imm_size;
3009 }
3010
3011 if (i.types[n] & Disp32S)
3012 sign = 1;
3013
3014 if (i.types[n] & (Disp16 | Disp64))
3015 {
3016 size = 2;
3017 if (i.types[n] & Disp64)
3018 size = 8;
3019 }
3020
3021 p = frag_more (size);
3022 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3023 i.op[n].disps, pcrel,
3024 reloc (size, pcrel, sign, i.reloc[n]));
3025 }
3026 }
3027 }
3028 }
3029
3030 /* Output immediate. */
3031 if (i.imm_operands)
3032 {
3033 register unsigned int n;
3034
3035 for (n = 0; n < i.operands; n++)
3036 {
3037 if (i.types[n] & Imm)
3038 {
3039 if (i.op[n].imms->X_op == O_constant)
3040 {
3041 int size;
3042 offsetT val;
3043
3044 size = 4;
3045 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3046 {
3047 size = 2;
3048 if (i.types[n] & (Imm8 | Imm8S))
3049 size = 1;
3050 else if (i.types[n] & Imm64)
3051 size = 8;
3052 }
3053 val = offset_in_range (i.op[n].imms->X_add_number,
3054 size);
3055 p = frag_more (size);
3056 md_number_to_chars (p, val, size);
3057 }
3058 else
3059 {
3060 /* Not absolute_section.
3061 Need a 32-bit fixup (don't support 8bit
3062 non-absolute imms). Try to support other
3063 sizes ... */
3064 RELOC_ENUM reloc_type;
3065 int size = 4;
3066 int sign = 0;
3067
3068 if ((i.types[n] & (Imm32S))
3069 && i.suffix == QWORD_MNEM_SUFFIX)
3070 sign = 1;
3071 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3072 {
3073 size = 2;
3074 if (i.types[n] & (Imm8 | Imm8S))
3075 size = 1;
3076 if (i.types[n] & Imm64)
3077 size = 8;
3078 }
3079
3080 p = frag_more (size);
3081 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3082#ifdef BFD_ASSEMBLER
3083 if (reloc_type == BFD_RELOC_32
3084 && GOT_symbol
3085 && GOT_symbol == i.op[n].imms->X_add_symbol
3086 && (i.op[n].imms->X_op == O_symbol
3087 || (i.op[n].imms->X_op == O_add
3088 && ((symbol_get_value_expression
3089 (i.op[n].imms->X_op_symbol)->X_op)
3090 == O_subtract))))
3091 {
3092 /* We don't support dynamic linking on x86-64 yet. */
3093 if (flag_code == CODE_64BIT)
3094 abort ();
3095 reloc_type = BFD_RELOC_386_GOTPC;
3096 i.op[n].imms->X_add_number += 3;
3097 }
3098#endif
3099 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3100 i.op[n].imms, 0, reloc_type);
3101 }
3102 }
3103 }
3104 }
3105 }
3106
3107#ifdef DEBUG386
3108 if (flag_debug)
3109 {
3110 pi (line, &i);
3111 }
3112#endif /* DEBUG386 */
3113 }
3114}
3115
3116
3117#ifndef LEX_AT
3118static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3119
3120/* Parse operands of the form
3121 <symbol>@GOTOFF+<nnn>
3122 and similar .plt or .got references.
3123
3124 If we find one, set up the correct relocation in RELOC and copy the
3125 input string, minus the `@GOTOFF' into a malloc'd buffer for
3126 parsing by the calling routine. Return this buffer, and if ADJUST
3127 is non-null set it to the length of the string we removed from the
3128 input line. Otherwise return NULL. */
3129static char *
3130lex_got (reloc, adjust)
3131 RELOC_ENUM *reloc;
3132 int *adjust;
3133{
3134 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3135 static const struct {
3136 const char *str;
3137 const RELOC_ENUM rel[NUM_FLAG_CODE];
3138 } gotrel[] = {
3139 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3140 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3141 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3142 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
3143 };
3144 char *cp;
3145 unsigned int j;
3146
3147 for (cp = input_line_pointer; *cp != '@'; cp++)
3148 if (is_end_of_line[(unsigned char) *cp])
3149 return NULL;
3150
3151 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3152 {
3153 int len;
3154
3155 len = strlen (gotrel[j].str);
3156 if (strncmp (cp + 1, gotrel[j].str, len) == 0)
3157 {
3158 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3159 {
3160 int first;
3161 char *tmpbuf;
3162
3163 *reloc = gotrel[j].rel[(unsigned int) flag_code];
3164
3165 if (GOT_symbol == NULL)
3166 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3167
3168 /* Replace the relocation token with ' ', so that
3169 errors like foo@GOTOFF1 will be detected. */
3170 first = cp - input_line_pointer;
3171 tmpbuf = xmalloc (strlen (input_line_pointer));
3172 memcpy (tmpbuf, input_line_pointer, first);
3173 tmpbuf[first] = ' ';
3174 strcpy (tmpbuf + first + 1, cp + 1 + len);
3175 if (adjust)
3176 *adjust = len;
3177 return tmpbuf;
3178 }
3179
3180 as_bad (_("@%s reloc is not supported in %s bit mode"),
3181 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3182 return NULL;
3183 }
3184 }
3185
3186 /* Might be a symbol version string. Don't as_bad here. */
3187 return NULL;
3188}
3189
3190/* x86_cons_fix_new is called via the expression parsing code when a
3191 reloc is needed. We use this hook to get the correct .got reloc. */
3192static RELOC_ENUM got_reloc = NO_RELOC;
3193
3194void
3195x86_cons_fix_new (frag, off, len, exp)
3196 fragS *frag;
3197 unsigned int off;
3198 unsigned int len;
3199 expressionS *exp;
3200{
3201 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3202 got_reloc = NO_RELOC;
3203 fix_new_exp (frag, off, len, exp, 0, r);
3204}
3205
3206void
3207x86_cons (exp, size)
3208 expressionS *exp;
3209 int size;
3210{
3211 if (size == 4)
3212 {
3213 /* Handle @GOTOFF and the like in an expression. */
3214 char *save;
3215 char *gotfree_input_line;
3216 int adjust;
3217
3218 save = input_line_pointer;
3219 gotfree_input_line = lex_got (&got_reloc, &adjust);
3220 if (gotfree_input_line)
3221 input_line_pointer = gotfree_input_line;
3222
3223 expression (exp);
3224
3225 if (gotfree_input_line)
3226 {
3227 /* expression () has merrily parsed up to the end of line,
3228 or a comma - in the wrong buffer. Transfer how far
3229 input_line_pointer has moved to the right buffer. */
3230 input_line_pointer = (save
3231 + (input_line_pointer - gotfree_input_line)
3232 + adjust);
3233 free (gotfree_input_line);
3234 }
3235 }
3236 else
3237 expression (exp);
3238}
3239#endif
3240
3241static int i386_immediate PARAMS ((char *));
3242
3243static int
3244i386_immediate (imm_start)
3245 char *imm_start;
3246{
3247 char *save_input_line_pointer;
3248#ifndef LEX_AT
3249 char *gotfree_input_line;
3250#endif
3251 segT exp_seg = 0;
3252 expressionS *exp;
3253
3254 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3255 {
3256 as_bad (_("only 1 or 2 immediate operands are allowed"));
3257 return 0;
3258 }
3259
3260 exp = &im_expressions[i.imm_operands++];
3261 i.op[this_operand].imms = exp;
3262
3263 if (is_space_char (*imm_start))
3264 ++imm_start;
3265
3266 save_input_line_pointer = input_line_pointer;
3267 input_line_pointer = imm_start;
3268
3269#ifndef LEX_AT
3270 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3271 if (gotfree_input_line)
3272 input_line_pointer = gotfree_input_line;
3273#endif
3274
3275 exp_seg = expression (exp);
3276
3277 SKIP_WHITESPACE ();
3278 if (*input_line_pointer)
3279 as_bad (_("junk `%s' after expression"), input_line_pointer);
3280
3281 input_line_pointer = save_input_line_pointer;
3282#ifndef LEX_AT
3283 if (gotfree_input_line)
3284 free (gotfree_input_line);
3285#endif
3286
3287 if (exp->X_op == O_absent || exp->X_op == O_big)
3288 {
3289 /* Missing or bad expr becomes absolute 0. */
3290 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3291 imm_start);
3292 exp->X_op = O_constant;
3293 exp->X_add_number = 0;
3294 exp->X_add_symbol = (symbolS *) 0;
3295 exp->X_op_symbol = (symbolS *) 0;
3296 }
3297 else if (exp->X_op == O_constant)
3298 {
3299 /* Size it properly later. */
3300 i.types[this_operand] |= Imm64;
3301 /* If BFD64, sign extend val. */
3302 if (!use_rela_relocations)
3303 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3304 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
3305 }
3306#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3307 else if (1
3308#ifdef BFD_ASSEMBLER
3309 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3310#endif
3311 && exp_seg != text_section
3312 && exp_seg != data_section
3313 && exp_seg != bss_section
3314 && exp_seg != undefined_section
3315#ifdef BFD_ASSEMBLER
3316 && !bfd_is_com_section (exp_seg)
3317#endif
3318 )
3319 {
3320#ifdef BFD_ASSEMBLER
3321 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3322#else
3323 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3324#endif
3325 return 0;
3326 }
3327#endif
3328 else
3329 {
3330 /* This is an address. The size of the address will be
3331 determined later, depending on destination register,
3332 suffix, or the default for the section. */
3333 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3334 }
3335
3336 return 1;
3337}
3338
3339static char *i386_scale PARAMS ((char *));
3340
3341static char *
3342i386_scale (scale)
3343 char *scale;
3344{
3345 offsetT val;
3346 char *save = input_line_pointer;
3347
3348 input_line_pointer = scale;
3349 val = get_absolute_expression ();
3350
3351 switch (val)
3352 {
3353 case 0:
3354 case 1:
3355 i.log2_scale_factor = 0;
3356 break;
3357 case 2:
3358 i.log2_scale_factor = 1;
3359 break;
3360 case 4:
3361 i.log2_scale_factor = 2;
3362 break;
3363 case 8:
3364 i.log2_scale_factor = 3;
3365 break;
3366 default:
3367 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3368 scale);
3369 input_line_pointer = save;
3370 return NULL;
3371 }
3372 if (i.log2_scale_factor != 0 && ! i.index_reg)
3373 {
3374 as_warn (_("scale factor of %d without an index register"),
3375 1 << i.log2_scale_factor);
3376#if SCALE1_WHEN_NO_INDEX
3377 i.log2_scale_factor = 0;
3378#endif
3379 }
3380 scale = input_line_pointer;
3381 input_line_pointer = save;
3382 return scale;
3383}
3384
3385static int i386_displacement PARAMS ((char *, char *));
3386
3387static int
3388i386_displacement (disp_start, disp_end)
3389 char *disp_start;
3390 char *disp_end;
3391{
3392 register expressionS *exp;
3393 segT exp_seg = 0;
3394 char *save_input_line_pointer;
3395#ifndef LEX_AT
3396 char *gotfree_input_line;
3397#endif
3398 int bigdisp = Disp32;
3399
3400 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3401 bigdisp = Disp16;
3402 if (flag_code == CODE_64BIT)
3403 bigdisp = Disp64;
3404 i.types[this_operand] |= bigdisp;
3405
3406 exp = &disp_expressions[i.disp_operands];
3407 i.op[this_operand].disps = exp;
3408 i.disp_operands++;
3409 save_input_line_pointer = input_line_pointer;
3410 input_line_pointer = disp_start;
3411 END_STRING_AND_SAVE (disp_end);
3412
3413#ifndef GCC_ASM_O_HACK
3414#define GCC_ASM_O_HACK 0
3415#endif
3416#if GCC_ASM_O_HACK
3417 END_STRING_AND_SAVE (disp_end + 1);
3418 if ((i.types[this_operand] & BaseIndex) != 0
3419 && displacement_string_end[-1] == '+')
3420 {
3421 /* This hack is to avoid a warning when using the "o"
3422 constraint within gcc asm statements.
3423 For instance:
3424
3425 #define _set_tssldt_desc(n,addr,limit,type) \
3426 __asm__ __volatile__ ( \
3427 "movw %w2,%0\n\t" \
3428 "movw %w1,2+%0\n\t" \
3429 "rorl $16,%1\n\t" \
3430 "movb %b1,4+%0\n\t" \
3431 "movb %4,5+%0\n\t" \
3432 "movb $0,6+%0\n\t" \
3433 "movb %h1,7+%0\n\t" \
3434 "rorl $16,%1" \
3435 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3436
3437 This works great except that the output assembler ends
3438 up looking a bit weird if it turns out that there is
3439 no offset. You end up producing code that looks like:
3440
3441 #APP
3442 movw $235,(%eax)
3443 movw %dx,2+(%eax)
3444 rorl $16,%edx
3445 movb %dl,4+(%eax)
3446 movb $137,5+(%eax)
3447 movb $0,6+(%eax)
3448 movb %dh,7+(%eax)
3449 rorl $16,%edx
3450 #NO_APP
3451
3452 So here we provide the missing zero. */
3453
3454 *displacement_string_end = '0';
3455 }
3456#endif
3457#ifndef LEX_AT
3458 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3459 if (gotfree_input_line)
3460 input_line_pointer = gotfree_input_line;
3461#endif
3462
3463 exp_seg = expression (exp);
3464
3465 SKIP_WHITESPACE ();
3466 if (*input_line_pointer)
3467 as_bad (_("junk `%s' after expression"), input_line_pointer);
3468#if GCC_ASM_O_HACK
3469 RESTORE_END_STRING (disp_end + 1);
3470#endif
3471 RESTORE_END_STRING (disp_end);
3472 input_line_pointer = save_input_line_pointer;
3473#ifndef LEX_AT
3474 if (gotfree_input_line)
3475 free (gotfree_input_line);
3476#endif
3477
3478#ifdef BFD_ASSEMBLER
3479 /* We do this to make sure that the section symbol is in
3480 the symbol table. We will ultimately change the relocation
3481 to be relative to the beginning of the section. */
3482 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3483 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3484 {
3485 if (exp->X_op != O_symbol)
3486 {
3487 as_bad (_("bad expression used with @%s"),
3488 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3489 ? "GOTPCREL"
3490 : "GOTOFF"));
3491 return 0;
3492 }
3493
3494 if (S_IS_LOCAL (exp->X_add_symbol)
3495 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3496 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
3497 exp->X_op = O_subtract;
3498 exp->X_op_symbol = GOT_symbol;
3499 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3500 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
3501 else
3502 i.reloc[this_operand] = BFD_RELOC_32;
3503 }
3504#endif
3505
3506 if (exp->X_op == O_absent || exp->X_op == O_big)
3507 {
3508 /* Missing or bad expr becomes absolute 0. */
3509 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3510 disp_start);
3511 exp->X_op = O_constant;
3512 exp->X_add_number = 0;
3513 exp->X_add_symbol = (symbolS *) 0;
3514 exp->X_op_symbol = (symbolS *) 0;
3515 }
3516
3517#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3518 if (exp->X_op != O_constant
3519#ifdef BFD_ASSEMBLER
3520 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3521#endif
3522 && exp_seg != text_section
3523 && exp_seg != data_section
3524 && exp_seg != bss_section
3525 && exp_seg != undefined_section)
3526 {
3527#ifdef BFD_ASSEMBLER
3528 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3529#else
3530 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3531#endif
3532 return 0;
3533 }
3534#endif
3535 else if (flag_code == CODE_64BIT)
3536 i.types[this_operand] |= Disp32S | Disp32;
3537 return 1;
3538}
3539
3540static int i386_index_check PARAMS ((const char *));
3541
3542/* Make sure the memory operand we've been dealt is valid.
3543 Return 1 on success, 0 on a failure. */
3544
3545static int
3546i386_index_check (operand_string)
3547 const char *operand_string;
3548{
3549 int ok;
3550#if INFER_ADDR_PREFIX
3551 int fudged = 0;
3552
3553 tryprefix:
3554#endif
3555 ok = 1;
3556 if (flag_code == CODE_64BIT)
3557 {
3558 /* 64bit checks. */
3559 if ((i.base_reg
3560 && ((i.base_reg->reg_type & Reg64) == 0)
3561 && (i.base_reg->reg_type != BaseIndex
3562 || i.index_reg))
3563 || (i.index_reg
3564 && ((i.index_reg->reg_type & (Reg64|BaseIndex))
3565 != (Reg64|BaseIndex))))
3566 ok = 0;
3567 }
3568 else
3569 {
3570 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3571 {
3572 /* 16bit checks. */
3573 if ((i.base_reg
3574 && ((i.base_reg->reg_type & (Reg16|BaseIndex|RegRex))
3575 != (Reg16|BaseIndex)))
3576 || (i.index_reg
3577 && (((i.index_reg->reg_type & (Reg16|BaseIndex))
3578 != (Reg16|BaseIndex))
3579 || ! (i.base_reg
3580 && i.base_reg->reg_num < 6
3581 && i.index_reg->reg_num >= 6
3582 && i.log2_scale_factor == 0))))
3583 ok = 0;
3584 }
3585 else
3586 {
3587 /* 32bit checks. */
3588 if ((i.base_reg
3589 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3590 || (i.index_reg
3591 && ((i.index_reg->reg_type & (Reg32|BaseIndex|RegRex))
3592 != (Reg32|BaseIndex))))
3593 ok = 0;
3594 }
3595 }
3596 if (!ok)
3597 {
3598#if INFER_ADDR_PREFIX
3599 if (flag_code != CODE_64BIT
3600 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
3601 {
3602 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3603 i.prefixes += 1;
3604 /* Change the size of any displacement too. At most one of
3605 Disp16 or Disp32 is set.
3606 FIXME. There doesn't seem to be any real need for separate
3607 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3608 Removing them would probably clean up the code quite a lot. */
3609 if (i.types[this_operand] & (Disp16|Disp32))
3610 i.types[this_operand] ^= (Disp16|Disp32);
3611 fudged = 1;
3612 goto tryprefix;
3613 }
3614 if (fudged)
3615 as_bad (_("`%s' is not a valid base/index expression"),
3616 operand_string);
3617 else
3618#endif
3619 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3620 operand_string,
3621 flag_code_names[flag_code]);
3622 return 0;
3623 }
3624 return 1;
3625}
3626
3627/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3628 on error. */
3629
3630static int
3631i386_operand (operand_string)
3632 char *operand_string;
3633{
3634 const reg_entry *r;
3635 char *end_op;
3636 char *op_string = operand_string;
3637
3638 if (is_space_char (*op_string))
3639 ++op_string;
3640
3641 /* We check for an absolute prefix (differentiating,
3642 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3643 if (*op_string == ABSOLUTE_PREFIX)
3644 {
3645 ++op_string;
3646 if (is_space_char (*op_string))
3647 ++op_string;
3648 i.types[this_operand] |= JumpAbsolute;
3649 }
3650
3651 /* Check if operand is a register. */
3652 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3653 && (r = parse_register (op_string, &end_op)) != NULL)
3654 {
3655 /* Check for a segment override by searching for ':' after a
3656 segment register. */
3657 op_string = end_op;
3658 if (is_space_char (*op_string))
3659 ++op_string;
3660 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3661 {
3662 switch (r->reg_num)
3663 {
3664 case 0:
3665 i.seg[i.mem_operands] = &es;
3666 break;
3667 case 1:
3668 i.seg[i.mem_operands] = &cs;
3669 break;
3670 case 2:
3671 i.seg[i.mem_operands] = &ss;
3672 break;
3673 case 3:
3674 i.seg[i.mem_operands] = &ds;
3675 break;
3676 case 4:
3677 i.seg[i.mem_operands] = &fs;
3678 break;
3679 case 5:
3680 i.seg[i.mem_operands] = &gs;
3681 break;
3682 }
3683
3684 /* Skip the ':' and whitespace. */
3685 ++op_string;
3686 if (is_space_char (*op_string))
3687 ++op_string;
3688
3689 if (!is_digit_char (*op_string)
3690 && !is_identifier_char (*op_string)
3691 && *op_string != '('
3692 && *op_string != ABSOLUTE_PREFIX)
3693 {
3694 as_bad (_("bad memory operand `%s'"), op_string);
3695 return 0;
3696 }
3697 /* Handle case of %es:*foo. */
3698 if (*op_string == ABSOLUTE_PREFIX)
3699 {
3700 ++op_string;
3701 if (is_space_char (*op_string))
3702 ++op_string;
3703 i.types[this_operand] |= JumpAbsolute;
3704 }
3705 goto do_memory_reference;
3706 }
3707 if (*op_string)
3708 {
3709 as_bad (_("junk `%s' after register"), op_string);
3710 return 0;
3711 }
3712 i.types[this_operand] |= r->reg_type & ~BaseIndex;
3713 i.op[this_operand].regs = r;
3714 i.reg_operands++;
3715 }
3716 else if (*op_string == REGISTER_PREFIX)
3717 {
3718 as_bad (_("bad register name `%s'"), op_string);
3719 return 0;
3720 }
3721 else if (*op_string == IMMEDIATE_PREFIX)
3722 {
3723 ++op_string;
3724 if (i.types[this_operand] & JumpAbsolute)
3725 {
3726 as_bad (_("immediate operand illegal with absolute jump"));
3727 return 0;
3728 }
3729 if (!i386_immediate (op_string))
3730 return 0;
3731 }
3732 else if (is_digit_char (*op_string)
3733 || is_identifier_char (*op_string)
3734 || *op_string == '(')
3735 {
3736 /* This is a memory reference of some sort. */
3737 char *base_string;
3738
3739 /* Start and end of displacement string expression (if found). */
3740 char *displacement_string_start;
3741 char *displacement_string_end;
3742
3743 do_memory_reference:
3744 if ((i.mem_operands == 1
3745 && (current_templates->start->opcode_modifier & IsString) == 0)
3746 || i.mem_operands == 2)
3747 {
3748 as_bad (_("too many memory references for `%s'"),
3749 current_templates->start->name);
3750 return 0;
3751 }
3752
3753 /* Check for base index form. We detect the base index form by
3754 looking for an ')' at the end of the operand, searching
3755 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3756 after the '('. */
3757 base_string = op_string + strlen (op_string);
3758
3759 --base_string;
3760 if (is_space_char (*base_string))
3761 --base_string;
3762
3763 /* If we only have a displacement, set-up for it to be parsed later. */
3764 displacement_string_start = op_string;
3765 displacement_string_end = base_string + 1;
3766
3767 if (*base_string == ')')
3768 {
3769 char *temp_string;
3770 unsigned int parens_balanced = 1;
3771 /* We've already checked that the number of left & right ()'s are
3772 equal, so this loop will not be infinite. */
3773 do
3774 {
3775 base_string--;
3776 if (*base_string == ')')
3777 parens_balanced++;
3778 if (*base_string == '(')
3779 parens_balanced--;
3780 }
3781 while (parens_balanced);
3782
3783 temp_string = base_string;
3784
3785 /* Skip past '(' and whitespace. */
3786 ++base_string;
3787 if (is_space_char (*base_string))
3788 ++base_string;
3789
3790 if (*base_string == ','
3791 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3792 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
3793 {
3794 displacement_string_end = temp_string;
3795
3796 i.types[this_operand] |= BaseIndex;
3797
3798 if (i.base_reg)
3799 {
3800 base_string = end_op;
3801 if (is_space_char (*base_string))
3802 ++base_string;
3803 }
3804
3805 /* There may be an index reg or scale factor here. */
3806 if (*base_string == ',')
3807 {
3808 ++base_string;
3809 if (is_space_char (*base_string))
3810 ++base_string;
3811
3812 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3813 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
3814 {
3815 base_string = end_op;
3816 if (is_space_char (*base_string))
3817 ++base_string;
3818 if (*base_string == ',')
3819 {
3820 ++base_string;
3821 if (is_space_char (*base_string))
3822 ++base_string;
3823 }
3824 else if (*base_string != ')')
3825 {
3826 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3827 operand_string);
3828 return 0;
3829 }
3830 }
3831 else if (*base_string == REGISTER_PREFIX)
3832 {
3833 as_bad (_("bad register name `%s'"), base_string);
3834 return 0;
3835 }
3836
3837 /* Check for scale factor. */
3838 if (*base_string != ')')
3839 {
3840 char *end_scale = i386_scale (base_string);
3841
3842 if (!end_scale)
3843 return 0;
3844
3845 base_string = end_scale;
3846 if (is_space_char (*base_string))
3847 ++base_string;
3848 if (*base_string != ')')
3849 {
3850 as_bad (_("expecting `)' after scale factor in `%s'"),
3851 operand_string);
3852 return 0;
3853 }
3854 }
3855 else if (!i.index_reg)
3856 {
3857 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3858 *base_string);
3859 return 0;
3860 }
3861 }
3862 else if (*base_string != ')')
3863 {
3864 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3865 operand_string);
3866 return 0;
3867 }
3868 }
3869 else if (*base_string == REGISTER_PREFIX)
3870 {
3871 as_bad (_("bad register name `%s'"), base_string);
3872 return 0;
3873 }
3874 }
3875
3876 /* If there's an expression beginning the operand, parse it,
3877 assuming displacement_string_start and
3878 displacement_string_end are meaningful. */
3879 if (displacement_string_start != displacement_string_end)
3880 {
3881 if (!i386_displacement (displacement_string_start,
3882 displacement_string_end))
3883 return 0;
3884 }
3885
3886 /* Special case for (%dx) while doing input/output op. */
3887 if (i.base_reg
3888 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
3889 && i.index_reg == 0
3890 && i.log2_scale_factor == 0
3891 && i.seg[i.mem_operands] == 0
3892 && (i.types[this_operand] & Disp) == 0)
3893 {
3894 i.types[this_operand] = InOutPortReg;
3895 return 1;
3896 }
3897
3898 if (i386_index_check (operand_string) == 0)
3899 return 0;
3900 i.mem_operands++;
3901 }
3902 else
3903 {
3904 /* It's not a memory operand; argh! */
3905 as_bad (_("invalid char %s beginning operand %d `%s'"),
3906 output_invalid (*op_string),
3907 this_operand + 1,
3908 op_string);
3909 return 0;
3910 }
3911 return 1; /* Normal return. */
3912}
3913
3914
3915/* md_estimate_size_before_relax()
3916
3917 Called just before relax() for rs_machine_dependent frags. The x86
3918 assembler uses these frags to handle variable size jump
3919 instructions.
3920
3921 Any symbol that is now undefined will not become defined.
3922 Return the correct fr_subtype in the frag.
3923 Return the initial "guess for variable size of frag" to caller.
3924 The guess is actually the growth beyond the fixed part. Whatever
3925 we do to grow the fixed or variable part contributes to our
3926 returned value. */
3927
3928int
3929md_estimate_size_before_relax (fragP, segment)
3930 register fragS *fragP;
3931 register segT segment;
3932{
3933 /* We've already got fragP->fr_subtype right; all we have to do is
3934 check for un-relaxable symbols. On an ELF system, we can't relax
3935 an externally visible symbol, because it may be overridden by a
3936 shared library. */
3937 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
3938#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3939 || S_IS_EXTERNAL (fragP->fr_symbol)
3940 || S_IS_WEAK (fragP->fr_symbol)
3941#endif
3942 )
3943 {
3944 /* Symbol is undefined in this segment, or we need to keep a
3945 reloc so that weak symbols can be overridden. */
3946 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
3947 RELOC_ENUM reloc_type;
3948 unsigned char *opcode;
3949 int old_fr_fix;
3950
3951 if (fragP->fr_var != NO_RELOC)
3952 reloc_type = fragP->fr_var;
3953 else if (size == 2)
3954 reloc_type = BFD_RELOC_16_PCREL;
3955 else
3956 reloc_type = BFD_RELOC_32_PCREL;
3957
3958 old_fr_fix = fragP->fr_fix;
3959 opcode = (unsigned char *) fragP->fr_opcode;
3960
3961 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
3962 {
3963 case UNCOND_JUMP:
3964 /* Make jmp (0xeb) a (d)word displacement jump. */
3965 opcode[0] = 0xe9;
3966 fragP->fr_fix += size;
3967 fix_new (fragP, old_fr_fix, size,
3968 fragP->fr_symbol,
3969 fragP->fr_offset, 1,
3970 reloc_type);
3971 break;
3972
3973 case COND_JUMP86:
3974 if (no_cond_jump_promotion)
3975 goto relax_guess;
3976
3977 if (size == 2)
3978 {
3979 /* Negate the condition, and branch past an
3980 unconditional jump. */
3981 opcode[0] ^= 1;
3982 opcode[1] = 3;
3983 /* Insert an unconditional jump. */
3984 opcode[2] = 0xe9;
3985 /* We added two extra opcode bytes, and have a two byte
3986 offset. */
3987 fragP->fr_fix += 2 + 2;
3988 fix_new (fragP, old_fr_fix + 2, 2,
3989 fragP->fr_symbol,
3990 fragP->fr_offset, 1,
3991 reloc_type);
3992 break;
3993 }
3994 /* Fall through. */
3995
3996 case COND_JUMP:
3997 if (no_cond_jump_promotion)
3998 goto relax_guess;
3999
4000 /* This changes the byte-displacement jump 0x7N
4001 to the (d)word-displacement jump 0x0f,0x8N. */
4002 opcode[1] = opcode[0] + 0x10;
4003 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4004 /* We've added an opcode byte. */
4005 fragP->fr_fix += 1 + size;
4006 fix_new (fragP, old_fr_fix + 1, size,
4007 fragP->fr_symbol,
4008 fragP->fr_offset, 1,
4009 reloc_type);
4010 break;
4011
4012 default:
4013 BAD_CASE (fragP->fr_subtype);
4014 break;
4015 }
4016 frag_wane (fragP);
4017 return fragP->fr_fix - old_fr_fix;
4018 }
4019
4020 relax_guess:
4021 /* Guess size depending on current relax state. Initially the relax
4022 state will correspond to a short jump and we return 1, because
4023 the variable part of the frag (the branch offset) is one byte
4024 long. However, we can relax a section more than once and in that
4025 case we must either set fr_subtype back to the unrelaxed state,
4026 or return the value for the appropriate branch. */
4027 return md_relax_table[fragP->fr_subtype].rlx_length;
4028}
4029
4030/* Called after relax() is finished.
4031
4032 In: Address of frag.
4033 fr_type == rs_machine_dependent.
4034 fr_subtype is what the address relaxed to.
4035
4036 Out: Any fixSs and constants are set up.
4037 Caller will turn frag into a ".space 0". */
4038
4039#ifndef BFD_ASSEMBLER
4040void
4041md_convert_frag (headers, sec, fragP)
4042 object_headers *headers ATTRIBUTE_UNUSED;
4043 segT sec ATTRIBUTE_UNUSED;
4044 register fragS *fragP;
4045#else
4046void
4047md_convert_frag (abfd, sec, fragP)
4048 bfd *abfd ATTRIBUTE_UNUSED;
4049 segT sec ATTRIBUTE_UNUSED;
4050 register fragS *fragP;
4051#endif
4052{
4053 register unsigned char *opcode;
4054 unsigned char *where_to_put_displacement = NULL;
4055 offsetT target_address;
4056 offsetT opcode_address;
4057 unsigned int extension = 0;
4058 offsetT displacement_from_opcode_start;
4059
4060 opcode = (unsigned char *) fragP->fr_opcode;
4061
4062 /* Address we want to reach in file space. */
4063 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4064#ifdef BFD_ASSEMBLER
4065 /* Not needed otherwise? */
4066 {
4067 /* Local symbols which have already been resolved have a NULL frag. */
4068 fragS *sym_frag = symbol_get_frag (fragP->fr_symbol);
4069 if (sym_frag)
4070 target_address += sym_frag->fr_address;
4071 }
4072#endif
4073
4074 /* Address opcode resides at in file space. */
4075 opcode_address = fragP->fr_address + fragP->fr_fix;
4076
4077 /* Displacement from opcode start to fill into instruction. */
4078 displacement_from_opcode_start = target_address - opcode_address;
4079
4080 if ((fragP->fr_subtype & BIG) == 0)
4081 {
4082 /* Don't have to change opcode. */
4083 extension = 1; /* 1 opcode + 1 displacement */
4084 where_to_put_displacement = &opcode[1];
4085 }
4086 else
4087 {
4088 if (no_cond_jump_promotion
4089 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4090 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4091
4092 switch (fragP->fr_subtype)
4093 {
4094 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4095 extension = 4; /* 1 opcode + 4 displacement */
4096 opcode[0] = 0xe9;
4097 where_to_put_displacement = &opcode[1];
4098 break;
4099
4100 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4101 extension = 2; /* 1 opcode + 2 displacement */
4102 opcode[0] = 0xe9;
4103 where_to_put_displacement = &opcode[1];
4104 break;
4105
4106 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4107 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4108 extension = 5; /* 2 opcode + 4 displacement */
4109 opcode[1] = opcode[0] + 0x10;
4110 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4111 where_to_put_displacement = &opcode[2];
4112 break;
4113
4114 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4115 extension = 3; /* 2 opcode + 2 displacement */
4116 opcode[1] = opcode[0] + 0x10;
4117 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4118 where_to_put_displacement = &opcode[2];
4119 break;
4120
4121 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4122 extension = 4;
4123 opcode[0] ^= 1;
4124 opcode[1] = 3;
4125 opcode[2] = 0xe9;
4126 where_to_put_displacement = &opcode[3];
4127 break;
4128
4129 default:
4130 BAD_CASE (fragP->fr_subtype);
4131 break;
4132 }
4133 }
4134
4135 /* Now put displacement after opcode. */
4136 md_number_to_chars ((char *) where_to_put_displacement,
4137 (valueT) (displacement_from_opcode_start - extension),
4138 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4139 fragP->fr_fix += extension;
4140}
4141
4142
4143/* Size of byte displacement jmp. */
4144int md_short_jump_size = 2;
4145
4146/* Size of dword displacement jmp. */
4147int md_long_jump_size = 5;
4148
4149/* Size of relocation record. */
4150const int md_reloc_size = 8;
4151
4152void
4153md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4154 char *ptr;
4155 addressT from_addr, to_addr;
4156 fragS *frag ATTRIBUTE_UNUSED;
4157 symbolS *to_symbol ATTRIBUTE_UNUSED;
4158{
4159 offsetT offset;
4160
4161 offset = to_addr - (from_addr + 2);
4162 /* Opcode for byte-disp jump. */
4163 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4164 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4165}
4166
4167void
4168md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4169 char *ptr;
4170 addressT from_addr, to_addr;
4171 fragS *frag ATTRIBUTE_UNUSED;
4172 symbolS *to_symbol ATTRIBUTE_UNUSED;
4173{
4174 offsetT offset;
4175
4176 offset = to_addr - (from_addr + 5);
4177 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4178 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4179}
4180
4181
4182/* Apply a fixup (fixS) to segment data, once it has been determined
4183 by our caller that we have all the info we need to fix it up.
4184
4185 On the 386, immediates, displacements, and data pointers are all in
4186 the same (little-endian) format, so we don't need to care about which
4187 we are handling. */
4188
4189int
4190md_apply_fix3 (fixP, valp, seg)
4191 /* The fix we're to put in. */
4192 fixS *fixP;
4193
4194 /* Pointer to the value of the bits. */
4195 valueT *valp;
4196
4197 /* Segment fix is from. */
4198 segT seg ATTRIBUTE_UNUSED;
4199{
4200 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4201 valueT value = *valp;
4202
4203#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4204 if (fixP->fx_pcrel)
4205 {
4206 switch (fixP->fx_r_type)
4207 {
4208 default:
4209 break;
4210
4211 case BFD_RELOC_32:
4212 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4213 break;
4214 case BFD_RELOC_16:
4215 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4216 break;
4217 case BFD_RELOC_8:
4218 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4219 break;
4220 }
4221 }
4222
4223 /* This is a hack. There should be a better way to handle this.
4224 This covers for the fact that bfd_install_relocation will
4225 subtract the current location (for partial_inplace, PC relative
4226 relocations); see more below. */
4227 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
4228 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4229 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4230 && fixP->fx_addsy && !use_rela_relocations)
4231 {
4232#ifndef OBJ_AOUT
4233 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4234#ifdef TE_PE
4235 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4236#endif
4237 )
4238 value += fixP->fx_where + fixP->fx_frag->fr_address;
4239#endif
4240#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4241 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4242 {
4243 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4244
4245 if ((fseg == seg
4246 || (symbol_section_p (fixP->fx_addsy)
4247 && fseg != absolute_section))
4248 && ! S_IS_EXTERNAL (fixP->fx_addsy)
4249 && ! S_IS_WEAK (fixP->fx_addsy)
4250 && S_IS_DEFINED (fixP->fx_addsy)
4251 && ! S_IS_COMMON (fixP->fx_addsy))
4252 {
4253 /* Yes, we add the values in twice. This is because
4254 bfd_perform_relocation subtracts them out again. I think
4255 bfd_perform_relocation is broken, but I don't dare change
4256 it. FIXME. */
4257 value += fixP->fx_where + fixP->fx_frag->fr_address;
4258 }
4259 }
4260#endif
4261#if defined (OBJ_COFF) && defined (TE_PE)
4262 /* For some reason, the PE format does not store a section
4263 address offset for a PC relative symbol. */
4264 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4265 value += md_pcrel_from (fixP);
4266#endif
4267 }
4268
4269 /* Fix a few things - the dynamic linker expects certain values here,
4270 and we must not dissappoint it. */
4271#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4272 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4273 && fixP->fx_addsy)
4274 switch (fixP->fx_r_type)
4275 {
4276 case BFD_RELOC_386_PLT32:
4277 case BFD_RELOC_X86_64_PLT32:
4278 /* Make the jump instruction point to the address of the operand. At
4279 runtime we merely add the offset to the actual PLT entry. */
4280 value = -4;
4281 break;
4282 case BFD_RELOC_386_GOTPC:
4283
4284/* This is tough to explain. We end up with this one if we have
4285 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4286 * here is to obtain the absolute address of the GOT, and it is strongly
4287 * preferable from a performance point of view to avoid using a runtime
4288 * relocation for this. The actual sequence of instructions often look
4289 * something like:
4290 *
4291 * call .L66
4292 * .L66:
4293 * popl %ebx
4294 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4295 *
4296 * The call and pop essentially return the absolute address of
4297 * the label .L66 and store it in %ebx. The linker itself will
4298 * ultimately change the first operand of the addl so that %ebx points to
4299 * the GOT, but to keep things simple, the .o file must have this operand
4300 * set so that it generates not the absolute address of .L66, but the
4301 * absolute address of itself. This allows the linker itself simply
4302 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4303 * added in, and the addend of the relocation is stored in the operand
4304 * field for the instruction itself.
4305 *
4306 * Our job here is to fix the operand so that it would add the correct
4307 * offset so that %ebx would point to itself. The thing that is tricky is
4308 * that .-.L66 will point to the beginning of the instruction, so we need
4309 * to further modify the operand so that it will point to itself.
4310 * There are other cases where you have something like:
4311 *
4312 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4313 *
4314 * and here no correction would be required. Internally in the assembler
4315 * we treat operands of this form as not being pcrel since the '.' is
4316 * explicitly mentioned, and I wonder whether it would simplify matters
4317 * to do it this way. Who knows. In earlier versions of the PIC patches,
4318 * the pcrel_adjust field was used to store the correction, but since the
4319 * expression is not pcrel, I felt it would be confusing to do it this
4320 * way. */
4321
4322 value -= 1;
4323 break;
4324 case BFD_RELOC_386_GOT32:
4325 case BFD_RELOC_X86_64_GOT32:
4326 value = 0; /* Fully resolved at runtime. No addend. */
4327 break;
4328 case BFD_RELOC_386_GOTOFF:
4329 case BFD_RELOC_X86_64_GOTPCREL:
4330 break;
4331
4332 case BFD_RELOC_VTABLE_INHERIT:
4333 case BFD_RELOC_VTABLE_ENTRY:
4334 fixP->fx_done = 0;
4335 return 1;
4336
4337 default:
4338 break;
4339 }
4340#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4341 *valp = value;
4342#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4343
4344#ifndef BFD_ASSEMBLER
4345 md_number_to_chars (p, value, fixP->fx_size);
4346#else
4347 /* Are we finished with this relocation now? */
4348 if (fixP->fx_addsy == 0 && fixP->fx_pcrel == 0)
4349 fixP->fx_done = 1;
4350 else if (use_rela_relocations)
4351 {
4352 fixP->fx_no_overflow = 1;
4353 value = 0;
4354 }
4355 md_number_to_chars (p, value, fixP->fx_size);
4356#endif
4357
4358 return 1;
4359}
4360
4361
4362#define MAX_LITTLENUMS 6
4363
4364/* Turn the string pointed to by litP into a floating point constant
4365 of type TYPE, and emit the appropriate bytes. The number of
4366 LITTLENUMS emitted is stored in *SIZEP. An error message is
4367 returned, or NULL on OK. */
4368
4369char *
4370md_atof (type, litP, sizeP)
4371 int type;
4372 char *litP;
4373 int *sizeP;
4374{
4375 int prec;
4376 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4377 LITTLENUM_TYPE *wordP;
4378 char *t;
4379
4380 switch (type)
4381 {
4382 case 'f':
4383 case 'F':
4384 prec = 2;
4385 break;
4386
4387 case 'd':
4388 case 'D':
4389 prec = 4;
4390 break;
4391
4392 case 'x':
4393 case 'X':
4394 prec = 5;
4395 break;
4396
4397 default:
4398 *sizeP = 0;
4399 return _("Bad call to md_atof ()");
4400 }
4401 t = atof_ieee (input_line_pointer, type, words);
4402 if (t)
4403 input_line_pointer = t;
4404
4405 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4406 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4407 the bigendian 386. */
4408 for (wordP = words + prec - 1; prec--;)
4409 {
4410 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4411 litP += sizeof (LITTLENUM_TYPE);
4412 }
4413 return 0;
4414}
4415
4416
4417char output_invalid_buf[8];
4418
4419static char *
4420output_invalid (c)
4421 int c;
4422{
4423 if (isprint (c))
4424 sprintf (output_invalid_buf, "'%c'", c);
4425 else
4426 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4427 return output_invalid_buf;
4428}
4429
4430/* REG_STRING starts *before* REGISTER_PREFIX. */
4431
4432static const reg_entry *
4433parse_register (reg_string, end_op)
4434 char *reg_string;
4435 char **end_op;
4436{
4437 char *s = reg_string;
4438 char *p;
4439 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4440 const reg_entry *r;
4441
4442 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4443 if (*s == REGISTER_PREFIX)
4444 ++s;
4445
4446 if (is_space_char (*s))
4447 ++s;
4448
4449 p = reg_name_given;
4450 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
4451 {
4452 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
4453 return (const reg_entry *) NULL;
4454 s++;
4455 }
4456
4457 /* For naked regs, make sure that we are not dealing with an identifier.
4458 This prevents confusing an identifier like `eax_var' with register
4459 `eax'. */
4460 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4461 return (const reg_entry *) NULL;
4462
4463 *end_op = s;
4464
4465 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4466
4467 /* Handle floating point regs, allowing spaces in the (i) part. */
4468 if (r == i386_regtab /* %st is first entry of table */)
4469 {
4470 if (is_space_char (*s))
4471 ++s;
4472 if (*s == '(')
4473 {
4474 ++s;
4475 if (is_space_char (*s))
4476 ++s;
4477 if (*s >= '0' && *s <= '7')
4478 {
4479 r = &i386_float_regtab[*s - '0'];
4480 ++s;
4481 if (is_space_char (*s))
4482 ++s;
4483 if (*s == ')')
4484 {
4485 *end_op = s + 1;
4486 return r;
4487 }
4488 }
4489 /* We have "%st(" then garbage. */
4490 return (const reg_entry *) NULL;
4491 }
4492 }
4493
4494 return r;
4495}
4496
4497
4498#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4499const char *md_shortopts = "kVQ:sq";
4500#else
4501const char *md_shortopts = "q";
4502#endif
4503
4504struct option md_longopts[] = {
4505#define OPTION_32 (OPTION_MD_BASE + 0)
4506 {"32", no_argument, NULL, OPTION_32},
4507#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4508#define OPTION_64 (OPTION_MD_BASE + 1)
4509 {"64", no_argument, NULL, OPTION_64},
4510#endif
4511 {NULL, no_argument, NULL, 0}
4512};
4513size_t md_longopts_size = sizeof (md_longopts);
4514
4515int
4516md_parse_option (c, arg)
4517 int c;
4518 char *arg ATTRIBUTE_UNUSED;
4519{
4520 switch (c)
4521 {
4522 case 'q':
4523 quiet_warnings = 1;
4524 break;
4525
4526#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4527 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4528 should be emitted or not. FIXME: Not implemented. */
4529 case 'Q':
4530 break;
4531
4532 /* -V: SVR4 argument to print version ID. */
4533 case 'V':
4534 print_version_id ();
4535 break;
4536
4537 /* -k: Ignore for FreeBSD compatibility. */
4538 case 'k':
4539 break;
4540
4541 case 's':
4542 /* -s: On i386 Solaris, this tells the native assembler to use
4543 .stab instead of .stab.excl. We always use .stab anyhow. */
4544 break;
4545
4546 case OPTION_64:
4547 {
4548 const char **list, **l;
4549
4550 list = bfd_target_list ();
4551 for (l = list; *l != NULL; l++)
4552 if (strcmp (*l, "elf64-x86-64") == 0)
4553 {
4554 default_arch = "x86_64";
4555 break;
4556 }
4557 if (*l == NULL)
4558 as_fatal (_("No compiled in support for x86_64"));
4559 free (list);
4560 }
4561 break;
4562#endif
4563
4564 case OPTION_32:
4565 default_arch = "i386";
4566 break;
4567
4568 default:
4569 return 0;
4570 }
4571 return 1;
4572}
4573
4574void
4575md_show_usage (stream)
4576 FILE *stream;
4577{
4578#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4579 fprintf (stream, _("\
4580 -Q ignored\n\
4581 -V print assembler version number\n\
4582 -k ignored\n\
4583 -q quieten some warnings\n\
4584 -s ignored\n"));
4585#else
4586 fprintf (stream, _("\
4587 -q quieten some warnings\n"));
4588#endif
4589}
4590
4591#ifdef BFD_ASSEMBLER
4592#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4593 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4594
4595/* Pick the target format to use. */
4596
4597const char *
4598i386_target_format ()
4599{
4600 if (!strcmp (default_arch, "x86_64"))
4601 set_code_flag (CODE_64BIT);
4602 else if (!strcmp (default_arch, "i386"))
4603 set_code_flag (CODE_32BIT);
4604 else
4605 as_fatal (_("Unknown architecture"));
4606 switch (OUTPUT_FLAVOR)
4607 {
4608#ifdef OBJ_MAYBE_AOUT
4609 case bfd_target_aout_flavour:
4610 return AOUT_TARGET_FORMAT;
4611#endif
4612#ifdef OBJ_MAYBE_COFF
4613 case bfd_target_coff_flavour:
4614 return "coff-i386";
4615#endif
4616#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4617 case bfd_target_elf_flavour:
4618 {
4619 if (flag_code == CODE_64BIT)
4620 use_rela_relocations = 1;
4621 return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386";
4622 }
4623#endif
4624 default:
4625 abort ();
4626 return NULL;
4627 }
4628}
4629
4630#endif /* OBJ_MAYBE_ more than one */
4631#endif /* BFD_ASSEMBLER */
4632
4633
4634symbolS *
4635md_undefined_symbol (name)
4636 char *name;
4637{
4638 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
4639 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
4640 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
4641 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
4642 {
4643 if (!GOT_symbol)
4644 {
4645 if (symbol_find (name))
4646 as_bad (_("GOT already in symbol table"));
4647 GOT_symbol = symbol_new (name, undefined_section,
4648 (valueT) 0, &zero_address_frag);
4649 };
4650 return GOT_symbol;
4651 }
4652 return 0;
4653}
4654
4655/* Round up a section size to the appropriate boundary. */
4656
4657valueT
4658md_section_align (segment, size)
4659 segT segment ATTRIBUTE_UNUSED;
4660 valueT size;
4661{
4662#ifdef BFD_ASSEMBLER
4663#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4664 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
4665 {
4666 /* For a.out, force the section size to be aligned. If we don't do
4667 this, BFD will align it for us, but it will not write out the
4668 final bytes of the section. This may be a bug in BFD, but it is
4669 easier to fix it here since that is how the other a.out targets
4670 work. */
4671 int align;
4672
4673 align = bfd_get_section_alignment (stdoutput, segment);
4674 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
4675 }
4676#endif
4677#endif
4678
4679 return size;
4680}
4681
4682/* On the i386, PC-relative offsets are relative to the start of the
4683 next instruction. That is, the address of the offset, plus its
4684 size, since the offset is always the last part of the insn. */
4685
4686long
4687md_pcrel_from (fixP)
4688 fixS *fixP;
4689{
4690 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
4691}
4692
4693#ifndef I386COFF
4694
4695static void
4696s_bss (ignore)
4697 int ignore ATTRIBUTE_UNUSED;
4698{
4699 register int temp;
4700
4701 temp = get_absolute_expression ();
4702 subseg_set (bss_section, (subsegT) temp);
4703 demand_empty_rest_of_line ();
4704}
4705
4706#endif
4707
4708#ifdef BFD_ASSEMBLER
4709
4710void
4711i386_validate_fix (fixp)
4712 fixS *fixp;
4713{
4714 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
4715 {
4716 /* GOTOFF relocation are nonsense in 64bit mode. */
4717 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
4718 {
4719 if (flag_code != CODE_64BIT)
4720 abort ();
4721 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
4722 }
4723 else
4724 {
4725 if (flag_code == CODE_64BIT)
4726 abort ();
4727 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
4728 }
4729 fixp->fx_subsy = 0;
4730 }
4731}
4732
4733arelent *
4734tc_gen_reloc (section, fixp)
4735 asection *section ATTRIBUTE_UNUSED;
4736 fixS *fixp;
4737{
4738 arelent *rel;
4739 bfd_reloc_code_real_type code;
4740
4741 switch (fixp->fx_r_type)
4742 {
4743 case BFD_RELOC_X86_64_PLT32:
4744 case BFD_RELOC_X86_64_GOT32:
4745 case BFD_RELOC_X86_64_GOTPCREL:
4746 case BFD_RELOC_386_PLT32:
4747 case BFD_RELOC_386_GOT32:
4748 case BFD_RELOC_386_GOTOFF:
4749 case BFD_RELOC_386_GOTPC:
4750 case BFD_RELOC_X86_64_32S:
4751 case BFD_RELOC_RVA:
4752 case BFD_RELOC_VTABLE_ENTRY:
4753 case BFD_RELOC_VTABLE_INHERIT:
4754 code = fixp->fx_r_type;
4755 break;
4756 default:
4757 if (fixp->fx_pcrel)
4758 {
4759 switch (fixp->fx_size)
4760 {
4761 default:
4762 as_bad (_("can not do %d byte pc-relative relocation"),
4763 fixp->fx_size);
4764 code = BFD_RELOC_32_PCREL;
4765 break;
4766 case 1: code = BFD_RELOC_8_PCREL; break;
4767 case 2: code = BFD_RELOC_16_PCREL; break;
4768 case 4: code = BFD_RELOC_32_PCREL; break;
4769 }
4770 }
4771 else
4772 {
4773 switch (fixp->fx_size)
4774 {
4775 default:
4776 as_bad (_("can not do %d byte relocation"), fixp->fx_size);
4777 code = BFD_RELOC_32;
4778 break;
4779 case 1: code = BFD_RELOC_8; break;
4780 case 2: code = BFD_RELOC_16; break;
4781 case 4: code = BFD_RELOC_32; break;
4782 case 8: code = BFD_RELOC_64; break;
4783 }
4784 }
4785 break;
4786 }
4787
4788 if (code == BFD_RELOC_32
4789 && GOT_symbol
4790 && fixp->fx_addsy == GOT_symbol)
4791 {
4792 /* We don't support GOTPC on 64bit targets. */
4793 if (flag_code == CODE_64BIT)
4794 abort ();
4795 code = BFD_RELOC_386_GOTPC;
4796 }
4797
4798 rel = (arelent *) xmalloc (sizeof (arelent));
4799 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
4800 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
4801
4802 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
4803 if (!use_rela_relocations)
4804 {
4805 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4806 vtable entry to be used in the relocation's section offset. */
4807 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4808 rel->address = fixp->fx_offset;
4809
4810 if (fixp->fx_pcrel)
4811 rel->addend = fixp->fx_addnumber;
4812 else
4813 rel->addend = 0;
4814 }
4815 /* Use the rela in 64bit mode. */
4816 else
4817 {
4818 rel->addend = fixp->fx_offset;
4819 if (fixp->fx_pcrel)
4820 rel->addend -= fixp->fx_size;
4821 }
4822
4823 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
4824 if (rel->howto == NULL)
4825 {
4826 as_bad_where (fixp->fx_file, fixp->fx_line,
4827 _("cannot represent relocation type %s"),
4828 bfd_get_reloc_code_name (code));
4829 /* Set howto to a garbage value so that we can keep going. */
4830 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
4831 assert (rel->howto != NULL);
4832 }
4833
4834 return rel;
4835}
4836
4837#else /* ! BFD_ASSEMBLER */
4838
4839#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4840void
4841tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4842 char *where;
4843 fixS *fixP;
4844 relax_addressT segment_address_in_file;
4845{
4846 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4847 Out: GNU LD relocation length code: 0, 1, or 2. */
4848
4849 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
4850 long r_symbolnum;
4851
4852 know (fixP->fx_addsy != NULL);
4853
4854 md_number_to_chars (where,
4855 (valueT) (fixP->fx_frag->fr_address
4856 + fixP->fx_where - segment_address_in_file),
4857 4);
4858
4859 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4860 ? S_GET_TYPE (fixP->fx_addsy)
4861 : fixP->fx_addsy->sy_number);
4862
4863 where[6] = (r_symbolnum >> 16) & 0x0ff;
4864 where[5] = (r_symbolnum >> 8) & 0x0ff;
4865 where[4] = r_symbolnum & 0x0ff;
4866 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
4867 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
4868 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
4869}
4870
4871#endif /* OBJ_AOUT or OBJ_BOUT. */
4872
4873#if defined (I386COFF)
4874
4875short
4876tc_coff_fix2rtype (fixP)
4877 fixS *fixP;
4878{
4879 if (fixP->fx_r_type == R_IMAGEBASE)
4880 return R_IMAGEBASE;
4881
4882 return (fixP->fx_pcrel ?
4883 (fixP->fx_size == 1 ? R_PCRBYTE :
4884 fixP->fx_size == 2 ? R_PCRWORD :
4885 R_PCRLONG) :
4886 (fixP->fx_size == 1 ? R_RELBYTE :
4887 fixP->fx_size == 2 ? R_RELWORD :
4888 R_DIR32));
4889}
4890
4891int
4892tc_coff_sizemachdep (frag)
4893 fragS *frag;
4894{
4895 if (frag->fr_next)
4896 return (frag->fr_next->fr_address - frag->fr_address);
4897 else
4898 return 0;
4899}
4900
4901#endif /* I386COFF */
4902
4903#endif /* ! BFD_ASSEMBLER */
4904
4905
4906/* Parse operands using Intel syntax. This implements a recursive descent
4907 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4908 Programmer's Guide.
4909
4910 FIXME: We do not recognize the full operand grammar defined in the MASM
4911 documentation. In particular, all the structure/union and
4912 high-level macro operands are missing.
4913
4914 Uppercase words are terminals, lower case words are non-terminals.
4915 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4916 bars '|' denote choices. Most grammar productions are implemented in
4917 functions called 'intel_<production>'.
4918
4919 Initial production is 'expr'.
4920
4921 addOp + | -
4922
4923 alpha [a-zA-Z]
4924
4925 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4926
4927 constant digits [[ radixOverride ]]
4928
4929 dataType BYTE | WORD | DWORD | QWORD | XWORD
4930
4931 digits decdigit
4932 | digits decdigit
4933 | digits hexdigit
4934
4935 decdigit [0-9]
4936
4937 e05 e05 addOp e06
4938 | e06
4939
4940 e06 e06 mulOp e09
4941 | e09
4942
4943 e09 OFFSET e10
4944 | e09 PTR e10
4945 | e09 : e10
4946 | e10
4947
4948 e10 e10 [ expr ]
4949 | e11
4950
4951 e11 ( expr )
4952 | [ expr ]
4953 | constant
4954 | dataType
4955 | id
4956 | $
4957 | register
4958
4959 => expr SHORT e05
4960 | e05
4961
4962 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4963 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4964
4965 hexdigit a | b | c | d | e | f
4966 | A | B | C | D | E | F
4967
4968 id alpha
4969 | id alpha
4970 | id decdigit
4971
4972 mulOp * | / | MOD
4973
4974 quote " | '
4975
4976 register specialRegister
4977 | gpRegister
4978 | byteRegister
4979
4980 segmentRegister CS | DS | ES | FS | GS | SS
4981
4982 specialRegister CR0 | CR2 | CR3
4983 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4984 | TR3 | TR4 | TR5 | TR6 | TR7
4985
4986 We simplify the grammar in obvious places (e.g., register parsing is
4987 done by calling parse_register) and eliminate immediate left recursion
4988 to implement a recursive-descent parser.
4989
4990 expr SHORT e05
4991 | e05
4992
4993 e05 e06 e05'
4994
4995 e05' addOp e06 e05'
4996 | Empty
4997
4998 e06 e09 e06'
4999
5000 e06' mulOp e09 e06'
5001 | Empty
5002
5003 e09 OFFSET e10 e09'
5004 | e10 e09'
5005
5006 e09' PTR e10 e09'
5007 | : e10 e09'
5008 | Empty
5009
5010 e10 e11 e10'
5011
5012 e10' [ expr ] e10'
5013 | Empty
5014
5015 e11 ( expr )
5016 | [ expr ]
5017 | BYTE
5018 | WORD
5019 | DWORD
5020 | QWORD
5021 | XWORD
5022 | .
5023 | $
5024 | register
5025 | id
5026 | constant */
5027
5028/* Parsing structure for the intel syntax parser. Used to implement the
5029 semantic actions for the operand grammar. */
5030struct intel_parser_s
5031 {
5032 char *op_string; /* The string being parsed. */
5033 int got_a_float; /* Whether the operand is a float. */
5034 int op_modifier; /* Operand modifier. */
5035 int is_mem; /* 1 if operand is memory reference. */
5036 const reg_entry *reg; /* Last register reference found. */
5037 char *disp; /* Displacement string being built. */
5038 };
5039
5040static struct intel_parser_s intel_parser;
5041
5042/* Token structure for parsing intel syntax. */
5043struct intel_token
5044 {
5045 int code; /* Token code. */
5046 const reg_entry *reg; /* Register entry for register tokens. */
5047 char *str; /* String representation. */
5048 };
5049
5050static struct intel_token cur_token, prev_token;
5051
5052/* Token codes for the intel parser. Since T_SHORT is already used
5053 by COFF, undefine it first to prevent a warning. */
5054#define T_NIL -1
5055#define T_CONST 1
5056#define T_REG 2
5057#define T_BYTE 3
5058#define T_WORD 4
5059#define T_DWORD 5
5060#define T_QWORD 6
5061#define T_XWORD 7
5062#undef T_SHORT
5063#define T_SHORT 8
5064#define T_OFFSET 9
5065#define T_PTR 10
5066#define T_ID 11
5067
5068/* Prototypes for intel parser functions. */
5069static int intel_match_token PARAMS ((int code));
5070static void intel_get_token PARAMS ((void));
5071static void intel_putback_token PARAMS ((void));
5072static int intel_expr PARAMS ((void));
5073static int intel_e05 PARAMS ((void));
5074static int intel_e05_1 PARAMS ((void));
5075static int intel_e06 PARAMS ((void));
5076static int intel_e06_1 PARAMS ((void));
5077static int intel_e09 PARAMS ((void));
5078static int intel_e09_1 PARAMS ((void));
5079static int intel_e10 PARAMS ((void));
5080static int intel_e10_1 PARAMS ((void));
5081static int intel_e11 PARAMS ((void));
5082
5083static int
5084i386_intel_operand (operand_string, got_a_float)
5085 char *operand_string;
5086 int got_a_float;
5087{
5088 int ret;
5089 char *p;
5090
5091 /* Initialize token holders. */
5092 cur_token.code = prev_token.code = T_NIL;
5093 cur_token.reg = prev_token.reg = NULL;
5094 cur_token.str = prev_token.str = NULL;
5095
5096 /* Initialize parser structure. */
5097 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
5098 if (p == NULL)
5099 abort ();
5100 strcpy (intel_parser.op_string, operand_string);
5101 intel_parser.got_a_float = got_a_float;
5102 intel_parser.op_modifier = -1;
5103 intel_parser.is_mem = 0;
5104 intel_parser.reg = NULL;
5105 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
5106 if (intel_parser.disp == NULL)
5107 abort ();
5108 intel_parser.disp[0] = '\0';
5109
5110 /* Read the first token and start the parser. */
5111 intel_get_token ();
5112 ret = intel_expr ();
5113
5114 if (ret)
5115 {
5116 /* If we found a memory reference, hand it over to i386_displacement
5117 to fill in the rest of the operand fields. */
5118 if (intel_parser.is_mem)
5119 {
5120 if ((i.mem_operands == 1
5121 && (current_templates->start->opcode_modifier & IsString) == 0)
5122 || i.mem_operands == 2)
5123 {
5124 as_bad (_("too many memory references for '%s'"),
5125 current_templates->start->name);
5126 ret = 0;
5127 }
5128 else
5129 {
5130 char *s = intel_parser.disp;
5131 i.mem_operands++;
5132
5133 /* Add the displacement expression. */
5134 if (*s != '\0')
5135 ret = i386_displacement (s, s + strlen (s))
5136 && i386_index_check (s);
5137 }
5138 }
5139
5140 /* Constant and OFFSET expressions are handled by i386_immediate. */
5141 else if (intel_parser.op_modifier == OFFSET_FLAT
5142 || intel_parser.reg == NULL)
5143 ret = i386_immediate (intel_parser.disp);
5144 }
5145
5146 free (p);
5147 free (intel_parser.disp);
5148
5149 return ret;
5150}
5151
5152/* expr SHORT e05
5153 | e05 */
5154static int
5155intel_expr ()
5156{
5157 /* expr SHORT e05 */
5158 if (cur_token.code == T_SHORT)
5159 {
5160 intel_parser.op_modifier = SHORT;
5161 intel_match_token (T_SHORT);
5162
5163 return (intel_e05 ());
5164 }
5165
5166 /* expr e05 */
5167 else
5168 return intel_e05 ();
5169}
5170
5171/* e05 e06 e05'
5172
5173 e05' addOp e06 e05'
5174 | Empty */
5175static int
5176intel_e05 ()
5177{
5178 return (intel_e06 () && intel_e05_1 ());
5179}
5180
5181static int
5182intel_e05_1 ()
5183{
5184 /* e05' addOp e06 e05' */
5185 if (cur_token.code == '+' || cur_token.code == '-')
5186 {
5187 strcat (intel_parser.disp, cur_token.str);
5188 intel_match_token (cur_token.code);
5189
5190 return (intel_e06 () && intel_e05_1 ());
5191 }
5192
5193 /* e05' Empty */
5194 else
5195 return 1;
5196}
5197
5198/* e06 e09 e06'
5199
5200 e06' mulOp e09 e06'
5201 | Empty */
5202static int
5203intel_e06 ()
5204{
5205 return (intel_e09 () && intel_e06_1 ());
5206}
5207
5208static int
5209intel_e06_1 ()
5210{
5211 /* e06' mulOp e09 e06' */
5212 if (cur_token.code == '*' || cur_token.code == '/')
5213 {
5214 strcat (intel_parser.disp, cur_token.str);
5215 intel_match_token (cur_token.code);
5216
5217 return (intel_e09 () && intel_e06_1 ());
5218 }
5219
5220 /* e06' Empty */
5221 else
5222 return 1;
5223}
5224
5225/* e09 OFFSET e10 e09'
5226 | e10 e09'
5227
5228 e09' PTR e10 e09'
5229 | : e10 e09'
5230 | Empty */
5231static int
5232intel_e09 ()
5233{
5234 /* e09 OFFSET e10 e09' */
5235 if (cur_token.code == T_OFFSET)
5236 {
5237 intel_parser.is_mem = 0;
5238 intel_parser.op_modifier = OFFSET_FLAT;
5239 intel_match_token (T_OFFSET);
5240
5241 return (intel_e10 () && intel_e09_1 ());
5242 }
5243
5244 /* e09 e10 e09' */
5245 else
5246 return (intel_e10 () && intel_e09_1 ());
5247}
5248
5249static int
5250intel_e09_1 ()
5251{
5252 /* e09' PTR e10 e09' */
5253 if (cur_token.code == T_PTR)
5254 {
5255 if (prev_token.code == T_BYTE)
5256 i.suffix = BYTE_MNEM_SUFFIX;
5257
5258 else if (prev_token.code == T_WORD)
5259 {
5260 if (intel_parser.got_a_float == 2) /* "fi..." */
5261 i.suffix = SHORT_MNEM_SUFFIX;
5262 else
5263 i.suffix = WORD_MNEM_SUFFIX;
5264 }
5265
5266 else if (prev_token.code == T_DWORD)
5267 {
5268 if (intel_parser.got_a_float == 1) /* "f..." */
5269 i.suffix = SHORT_MNEM_SUFFIX;
5270 else
5271 i.suffix = LONG_MNEM_SUFFIX;
5272 }
5273
5274 else if (prev_token.code == T_QWORD)
5275 {
5276 if (intel_parser.got_a_float == 1) /* "f..." */
5277 i.suffix = LONG_MNEM_SUFFIX;
5278 else
5279 i.suffix = QWORD_MNEM_SUFFIX;
5280 }
5281
5282 else if (prev_token.code == T_XWORD)
5283 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5284
5285 else
5286 {
5287 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5288 return 0;
5289 }
5290
5291 intel_match_token (T_PTR);
5292
5293 return (intel_e10 () && intel_e09_1 ());
5294 }
5295
5296 /* e09 : e10 e09' */
5297 else if (cur_token.code == ':')
5298 {
5299 /* Mark as a memory operand only if it's not already known to be an
5300 offset expression. */
5301 if (intel_parser.op_modifier != OFFSET_FLAT)
5302 intel_parser.is_mem = 1;
5303
5304 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5305 }
5306
5307 /* e09' Empty */
5308 else
5309 return 1;
5310}
5311
5312/* e10 e11 e10'
5313
5314 e10' [ expr ] e10'
5315 | Empty */
5316static int
5317intel_e10 ()
5318{
5319 return (intel_e11 () && intel_e10_1 ());
5320}
5321
5322static int
5323intel_e10_1 ()
5324{
5325 /* e10' [ expr ] e10' */
5326 if (cur_token.code == '[')
5327 {
5328 intel_match_token ('[');
5329
5330 /* Mark as a memory operand only if it's not already known to be an
5331 offset expression. If it's an offset expression, we need to keep
5332 the brace in. */
5333 if (intel_parser.op_modifier != OFFSET_FLAT)
5334 intel_parser.is_mem = 1;
5335 else
5336 strcat (intel_parser.disp, "[");
5337
5338 /* Add a '+' to the displacement string if necessary. */
5339 if (*intel_parser.disp != '\0'
5340 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5341 strcat (intel_parser.disp, "+");
5342
5343 if (intel_expr () && intel_match_token (']'))
5344 {
5345 /* Preserve brackets when the operand is an offset expression. */
5346 if (intel_parser.op_modifier == OFFSET_FLAT)
5347 strcat (intel_parser.disp, "]");
5348
5349 return intel_e10_1 ();
5350 }
5351 else
5352 return 0;
5353 }
5354
5355 /* e10' Empty */
5356 else
5357 return 1;
5358}
5359
5360/* e11 ( expr )
5361 | [ expr ]
5362 | BYTE
5363 | WORD
5364 | DWORD
5365 | QWORD
5366 | XWORD
5367 | $
5368 | .
5369 | register
5370 | id
5371 | constant */
5372static int
5373intel_e11 ()
5374{
5375 /* e11 ( expr ) */
5376 if (cur_token.code == '(')
5377 {
5378 intel_match_token ('(');
5379 strcat (intel_parser.disp, "(");
5380
5381 if (intel_expr () && intel_match_token (')'))
5382 {
5383 strcat (intel_parser.disp, ")");
5384 return 1;
5385 }
5386 else
5387 return 0;
5388 }
5389
5390 /* e11 [ expr ] */
5391 else if (cur_token.code == '[')
5392 {
5393 intel_match_token ('[');
5394
5395 /* Mark as a memory operand only if it's not already known to be an
5396 offset expression. If it's an offset expression, we need to keep
5397 the brace in. */
5398 if (intel_parser.op_modifier != OFFSET_FLAT)
5399 intel_parser.is_mem = 1;
5400 else
5401 strcat (intel_parser.disp, "[");
5402
5403 /* Operands for jump/call inside brackets denote absolute addresses. */
5404 if (current_templates->start->opcode_modifier & Jump
5405 || current_templates->start->opcode_modifier & JumpDword
5406 || current_templates->start->opcode_modifier & JumpByte
5407 || current_templates->start->opcode_modifier & JumpInterSegment)
5408 i.types[this_operand] |= JumpAbsolute;
5409
5410 /* Add a '+' to the displacement string if necessary. */
5411 if (*intel_parser.disp != '\0'
5412 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5413 strcat (intel_parser.disp, "+");
5414
5415 if (intel_expr () && intel_match_token (']'))
5416 {
5417 /* Preserve brackets when the operand is an offset expression. */
5418 if (intel_parser.op_modifier == OFFSET_FLAT)
5419 strcat (intel_parser.disp, "]");
5420
5421 return 1;
5422 }
5423 else
5424 return 0;
5425 }
5426
5427 /* e11 BYTE
5428 | WORD
5429 | DWORD
5430 | QWORD
5431 | XWORD */
5432 else if (cur_token.code == T_BYTE
5433 || cur_token.code == T_WORD
5434 || cur_token.code == T_DWORD
5435 || cur_token.code == T_QWORD
5436 || cur_token.code == T_XWORD)
5437 {
5438 intel_match_token (cur_token.code);
5439
5440 return 1;
5441 }
5442
5443 /* e11 $
5444 | . */
5445 else if (cur_token.code == '$' || cur_token.code == '.')
5446 {
5447 strcat (intel_parser.disp, cur_token.str);
5448 intel_match_token (cur_token.code);
5449
5450 /* Mark as a memory operand only if it's not already known to be an
5451 offset expression. */
5452 if (intel_parser.op_modifier != OFFSET_FLAT)
5453 intel_parser.is_mem = 1;
5454
5455 return 1;
5456 }
5457
5458 /* e11 register */
5459 else if (cur_token.code == T_REG)
5460 {
5461 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5462
5463 intel_match_token (T_REG);
5464
5465 /* Check for segment change. */
5466 if (cur_token.code == ':')
5467 {
5468 if (reg->reg_type & (SReg2 | SReg3))
5469 {
5470 switch (reg->reg_num)
5471 {
5472 case 0:
5473 i.seg[i.mem_operands] = &es;
5474 break;
5475 case 1:
5476 i.seg[i.mem_operands] = &cs;
5477 break;
5478 case 2:
5479 i.seg[i.mem_operands] = &ss;
5480 break;
5481 case 3:
5482 i.seg[i.mem_operands] = &ds;
5483 break;
5484 case 4:
5485 i.seg[i.mem_operands] = &fs;
5486 break;
5487 case 5:
5488 i.seg[i.mem_operands] = &gs;
5489 break;
5490 }
5491 }
5492 else
5493 {
5494 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5495 return 0;
5496 }
5497 }
5498
5499 /* Not a segment register. Check for register scaling. */
5500 else if (cur_token.code == '*')
5501 {
5502 if (!intel_parser.is_mem)
5503 {
5504 as_bad (_("Register scaling only allowed in memory operands."));
5505 return 0;
5506 }
5507
5508 /* What follows must be a valid scale. */
5509 if (intel_match_token ('*')
5510 && strchr ("01248", *cur_token.str))
5511 {
5512 i.index_reg = reg;
5513 i.types[this_operand] |= BaseIndex;
5514
5515 /* Set the scale after setting the register (otherwise,
5516 i386_scale will complain) */
5517 i386_scale (cur_token.str);
5518 intel_match_token (T_CONST);
5519 }
5520 else
5521 {
5522 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5523 cur_token.str);
5524 return 0;
5525 }
5526 }
5527
5528 /* No scaling. If this is a memory operand, the register is either a
5529 base register (first occurrence) or an index register (second
5530 occurrence). */
5531 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5532 {
5533 if (i.base_reg && i.index_reg)
5534 {
5535 as_bad (_("Too many register references in memory operand.\n"));
5536 return 0;
5537 }
5538
5539 if (i.base_reg == NULL)
5540 i.base_reg = reg;
5541 else
5542 i.index_reg = reg;
5543
5544 i.types[this_operand] |= BaseIndex;
5545 }
5546
5547 /* Offset modifier. Add the register to the displacement string to be
5548 parsed as an immediate expression after we're done. */
5549 else if (intel_parser.op_modifier == OFFSET_FLAT)
5550 strcat (intel_parser.disp, reg->reg_name);
5551
5552 /* It's neither base nor index nor offset. */
5553 else
5554 {
5555 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5556 i.op[this_operand].regs = reg;
5557 i.reg_operands++;
5558 }
5559
5560 /* Since registers are not part of the displacement string (except
5561 when we're parsing offset operands), we may need to remove any
5562 preceding '+' from the displacement string. */
5563 if (*intel_parser.disp != '\0'
5564 && intel_parser.op_modifier != OFFSET_FLAT)
5565 {
5566 char *s = intel_parser.disp;
5567 s += strlen (s) - 1;
5568 if (*s == '+')
5569 *s = '\0';
5570 }
5571
5572 return 1;
5573 }
5574
5575 /* e11 id */
5576 else if (cur_token.code == T_ID)
5577 {
5578 /* Add the identifier to the displacement string. */
5579 strcat (intel_parser.disp, cur_token.str);
5580 intel_match_token (T_ID);
5581
5582 /* The identifier represents a memory reference only if it's not
5583 preceded by an offset modifier. */
5584 if (intel_parser.op_modifier != OFFSET_FLAT)
5585 intel_parser.is_mem = 1;
5586
5587 return 1;
5588 }
5589
5590 /* e11 constant */
5591 else if (cur_token.code == T_CONST
5592 || cur_token.code == '-'
5593 || cur_token.code == '+')
5594 {
5595 char *save_str;
5596
5597 /* Allow constants that start with `+' or `-'. */
5598 if (cur_token.code == '-' || cur_token.code == '+')
5599 {
5600 strcat (intel_parser.disp, cur_token.str);
5601 intel_match_token (cur_token.code);
5602 if (cur_token.code != T_CONST)
5603 {
5604 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5605 cur_token.str);
5606 return 0;
5607 }
5608 }
5609
5610 save_str = (char *) malloc (strlen (cur_token.str) + 1);
5611 if (save_str == NULL)
5612 abort ();
5613 strcpy (save_str, cur_token.str);
5614
5615 /* Get the next token to check for register scaling. */
5616 intel_match_token (cur_token.code);
5617
5618 /* Check if this constant is a scaling factor for an index register. */
5619 if (cur_token.code == '*')
5620 {
5621 if (intel_match_token ('*') && cur_token.code == T_REG)
5622 {
5623 if (!intel_parser.is_mem)
5624 {
5625 as_bad (_("Register scaling only allowed in memory operands."));
5626 return 0;
5627 }
5628
5629 /* The constant is followed by `* reg', so it must be
5630 a valid scale. */
5631 if (strchr ("01248", *save_str))
5632 {
5633 i.index_reg = cur_token.reg;
5634 i.types[this_operand] |= BaseIndex;
5635
5636 /* Set the scale after setting the register (otherwise,
5637 i386_scale will complain) */
5638 i386_scale (save_str);
5639 intel_match_token (T_REG);
5640
5641 /* Since registers are not part of the displacement
5642 string, we may need to remove any preceding '+' from
5643 the displacement string. */
5644 if (*intel_parser.disp != '\0')
5645 {
5646 char *s = intel_parser.disp;
5647 s += strlen (s) - 1;
5648 if (*s == '+')
5649 *s = '\0';
5650 }
5651
5652 free (save_str);
5653
5654 return 1;
5655 }
5656 else
5657 return 0;
5658 }
5659
5660 /* The constant was not used for register scaling. Since we have
5661 already consumed the token following `*' we now need to put it
5662 back in the stream. */
5663 else
5664 intel_putback_token ();
5665 }
5666
5667 /* Add the constant to the displacement string. */
5668 strcat (intel_parser.disp, save_str);
5669 free (save_str);
5670
5671 return 1;
5672 }
5673
5674 as_bad (_("Unrecognized token '%s'"), cur_token.str);
5675 return 0;
5676}
5677
5678/* Match the given token against cur_token. If they match, read the next
5679 token from the operand string. */
5680static int
5681intel_match_token (code)
5682 int code;
5683{
5684 if (cur_token.code == code)
5685 {
5686 intel_get_token ();
5687 return 1;
5688 }
5689 else
5690 {
5691 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
5692 return 0;
5693 }
5694}
5695
5696/* Read a new token from intel_parser.op_string and store it in cur_token. */
5697static void
5698intel_get_token ()
5699{
5700 char *end_op;
5701 const reg_entry *reg;
5702 struct intel_token new_token;
5703
5704 new_token.code = T_NIL;
5705 new_token.reg = NULL;
5706 new_token.str = NULL;
5707
5708 /* Free the memory allocated to the previous token and move
5709 cur_token to prev_token. */
5710 if (prev_token.str)
5711 free (prev_token.str);
5712
5713 prev_token = cur_token;
5714
5715 /* Skip whitespace. */
5716 while (is_space_char (*intel_parser.op_string))
5717 intel_parser.op_string++;
5718
5719 /* Return an empty token if we find nothing else on the line. */
5720 if (*intel_parser.op_string == '\0')
5721 {
5722 cur_token = new_token;
5723 return;
5724 }
5725
5726 /* The new token cannot be larger than the remainder of the operand
5727 string. */
5728 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
5729 if (new_token.str == NULL)
5730 abort ();
5731 new_token.str[0] = '\0';
5732
5733 if (strchr ("0123456789", *intel_parser.op_string))
5734 {
5735 char *p = new_token.str;
5736 char *q = intel_parser.op_string;
5737 new_token.code = T_CONST;
5738
5739 /* Allow any kind of identifier char to encompass floating point and
5740 hexadecimal numbers. */
5741 while (is_identifier_char (*q))
5742 *p++ = *q++;
5743 *p = '\0';
5744
5745 /* Recognize special symbol names [0-9][bf]. */
5746 if (strlen (intel_parser.op_string) == 2
5747 && (intel_parser.op_string[1] == 'b'
5748 || intel_parser.op_string[1] == 'f'))
5749 new_token.code = T_ID;
5750 }
5751
5752 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
5753 {
5754 new_token.code = *intel_parser.op_string;
5755 new_token.str[0] = *intel_parser.op_string;
5756 new_token.str[1] = '\0';
5757 }
5758
5759 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
5760 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
5761 {
5762 new_token.code = T_REG;
5763 new_token.reg = reg;
5764
5765 if (*intel_parser.op_string == REGISTER_PREFIX)
5766 {
5767 new_token.str[0] = REGISTER_PREFIX;
5768 new_token.str[1] = '\0';
5769 }
5770
5771 strcat (new_token.str, reg->reg_name);
5772 }
5773
5774 else if (is_identifier_char (*intel_parser.op_string))
5775 {
5776 char *p = new_token.str;
5777 char *q = intel_parser.op_string;
5778
5779 /* A '.' or '$' followed by an identifier char is an identifier.
5780 Otherwise, it's operator '.' followed by an expression. */
5781 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
5782 {
5783 new_token.code = *q;
5784 new_token.str[0] = *q;
5785 new_token.str[1] = '\0';
5786 }
5787 else
5788 {
5789 while (is_identifier_char (*q) || *q == '@')
5790 *p++ = *q++;
5791 *p = '\0';
5792
5793 if (strcasecmp (new_token.str, "BYTE") == 0)
5794 new_token.code = T_BYTE;
5795
5796 else if (strcasecmp (new_token.str, "WORD") == 0)
5797 new_token.code = T_WORD;
5798
5799 else if (strcasecmp (new_token.str, "DWORD") == 0)
5800 new_token.code = T_DWORD;
5801
5802 else if (strcasecmp (new_token.str, "QWORD") == 0)
5803 new_token.code = T_QWORD;
5804
5805 else if (strcasecmp (new_token.str, "XWORD") == 0)
5806 new_token.code = T_XWORD;
5807
5808 else if (strcasecmp (new_token.str, "PTR") == 0)
5809 new_token.code = T_PTR;
5810
5811 else if (strcasecmp (new_token.str, "SHORT") == 0)
5812 new_token.code = T_SHORT;
5813
5814 else if (strcasecmp (new_token.str, "OFFSET") == 0)
5815 {
5816 new_token.code = T_OFFSET;
5817
5818 /* ??? This is not mentioned in the MASM grammar but gcc
5819 makes use of it with -mintel-syntax. OFFSET may be
5820 followed by FLAT: */
5821 if (strncasecmp (q, " FLAT:", 6) == 0)
5822 strcat (new_token.str, " FLAT:");
5823 }
5824
5825 /* ??? This is not mentioned in the MASM grammar. */
5826 else if (strcasecmp (new_token.str, "FLAT") == 0)
5827 new_token.code = T_OFFSET;
5828
5829 else
5830 new_token.code = T_ID;
5831 }
5832 }
5833
5834 else
5835 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
5836
5837 intel_parser.op_string += strlen (new_token.str);
5838 cur_token = new_token;
5839}
5840
5841/* Put cur_token back into the token stream and make cur_token point to
5842 prev_token. */
5843static void
5844intel_putback_token ()
5845{
5846 intel_parser.op_string -= strlen (cur_token.str);
5847 free (cur_token.str);
5848 cur_token = prev_token;
5849
5850 /* Forget prev_token. */
5851 prev_token.code = T_NIL;
5852 prev_token.reg = NULL;
5853 prev_token.str = NULL;
5854}
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